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Searched refs:WREG32 (Results 1 - 25 of 323) sorted by relevance

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/kernel/linux/linux-5.10/drivers/misc/habanalabs/goya/
H A Dgoya_coresight.c245 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); in goya_config_stm()
253 WREG32(base_reg + 0xE80, 0x80004); in goya_config_stm()
254 WREG32(base_reg + 0xD64, 7); in goya_config_stm()
255 WREG32(base_reg + 0xD60, 0); in goya_config_stm()
256 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); in goya_config_stm()
257 WREG32(base_reg + 0xD20, lower_32_bits(input->sp_mask)); in goya_config_stm()
258 WREG32(base_reg + 0xD60, 1); in goya_config_stm()
259 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask)); in goya_config_stm()
260 WREG32(base_reg + 0xD20, upper_32_bits(input->sp_mask)); in goya_config_stm()
261 WREG32(base_re in goya_config_stm()
[all...]
H A Dgoya_security.c23 WREG32(pb_addr, 0); in goya_pb_set_block()
81 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
104 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
128 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
160 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
180 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
194 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
210 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
228 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
251 WREG32(pb_add in goya_init_mme_protection_bits()
[all...]
H A Dgoya.c657 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_FULLY_TRUSTED); in goya_qman0_set_security()
659 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_PARTLY_TRUSTED); in goya_qman0_set_security()
747 WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size)); in goya_late_init()
756 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, in goya_late_init()
921 WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address)); in goya_init_dma_qman()
922 WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address)); in goya_init_dma_qman()
924 WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH)); in goya_init_dma_qman()
925 WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0); in goya_init_dma_qman()
926 WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0); in goya_init_dma_qman()
928 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_L in goya_init_dma_qman()
[all...]
/kernel/linux/linux-6.6/drivers/accel/habanalabs/goya/
H A Dgoya_coresight.c243 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); in goya_config_stm()
251 WREG32(base_reg + 0xE80, 0x80004); in goya_config_stm()
252 WREG32(base_reg + 0xD64, 7); in goya_config_stm()
253 WREG32(base_reg + 0xD60, 0); in goya_config_stm()
254 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); in goya_config_stm()
255 WREG32(base_reg + 0xD20, lower_32_bits(input->sp_mask)); in goya_config_stm()
256 WREG32(base_reg + 0xD60, 1); in goya_config_stm()
257 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask)); in goya_config_stm()
258 WREG32(base_reg + 0xD20, upper_32_bits(input->sp_mask)); in goya_config_stm()
259 WREG32(base_re in goya_config_stm()
[all...]
H A Dgoya_security.c23 WREG32(pb_addr, 0); in goya_pb_set_block()
81 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
104 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
128 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
160 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
180 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
194 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
210 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
228 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
251 WREG32(pb_add in goya_init_mme_protection_bits()
[all...]
H A Dgoya.c734 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_FULLY_TRUSTED); in goya_qman0_set_security()
736 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_PARTLY_TRUSTED); in goya_qman0_set_security()
895 WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size)); in goya_late_init()
1106 WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address)); in goya_init_dma_qman()
1107 WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address)); in goya_init_dma_qman()
1109 WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH)); in goya_init_dma_qman()
1110 WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0); in goya_init_dma_qman()
1111 WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0); in goya_init_dma_qman()
1113 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo); in goya_init_dma_qman()
1114 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_H in goya_init_dma_qman()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Drv515.c153 WREG32(R_000300_VGA_RENDER_CONTROL, in rv515_vga_render_disable()
218 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); in rv515_mc_rreg()
220 WREG32(MC_IND_INDEX, 0); in rv515_mc_rreg()
231 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); in rv515_mc_wreg()
232 WREG32(MC_IND_DATA, (v)); in rv515_mc_wreg()
233 WREG32(MC_IND_INDEX, 0); in rv515_mc_wreg()
307 WREG32(R_000300_VGA_RENDER_CONTROL, 0); in rv515_mc_stop()
316 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in rv515_mc_stop()
318 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); in rv515_mc_stop()
319 WREG32(AVIVO_D1CRTC_UPDATE_LOC in rv515_mc_stop()
[all...]
H A Dradeon_bios.c276 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); in ni_read_disabled_bios()
279 WREG32(AVIVO_D1VGA_CONTROL, in ni_read_disabled_bios()
282 WREG32(AVIVO_D2VGA_CONTROL, in ni_read_disabled_bios()
285 WREG32(AVIVO_VGA_RENDER_CONTROL, in ni_read_disabled_bios()
288 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); in ni_read_disabled_bios()
293 WREG32(R600_BUS_CNTL, bus_cntl); in ni_read_disabled_bios()
295 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); in ni_read_disabled_bios()
296 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); in ni_read_disabled_bios()
297 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); in ni_read_disabled_bios()
299 WREG32(R600_ROM_CNT in ni_read_disabled_bios()
[all...]
H A Dvce_v2_0.c45 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_sw_cg()
49 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
53 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
55 WREG32(VCE_CGTT_CLK_OVERRIDE, 0); in vce_v2_0_set_sw_cg()
60 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_sw_cg()
65 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
69 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
85 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_dyn_cg()
91 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_dyn_cg()
96 WREG32(VCE_UENC_REG_CLOCK_GATIN in vce_v2_0_set_dyn_cg()
[all...]
H A Duvd_v1_0.c70 WREG32(UVD_RBC_RB_WPTR, ring->wptr); in uvd_v1_0_set_wptr()
123 WREG32(UVD_VCPU_CACHE_OFFSET0, addr); in uvd_v1_0_resume()
124 WREG32(UVD_VCPU_CACHE_SIZE0, size); in uvd_v1_0_resume()
128 WREG32(UVD_VCPU_CACHE_OFFSET1, addr); in uvd_v1_0_resume()
129 WREG32(UVD_VCPU_CACHE_SIZE1, size); in uvd_v1_0_resume()
134 WREG32(UVD_VCPU_CACHE_OFFSET2, addr); in uvd_v1_0_resume()
135 WREG32(UVD_VCPU_CACHE_SIZE2, size); in uvd_v1_0_resume()
139 WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); in uvd_v1_0_resume()
143 WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); in uvd_v1_0_resume()
145 WREG32(UVD_FW_STAR in uvd_v1_0_resume()
[all...]
H A Dvce_v1_0.c97 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_set_wptr()
99 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_set_wptr()
109 WREG32(VCE_CLOCK_GATING_A, tmp); in vce_v1_0_enable_mgcg()
114 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v1_0_enable_mgcg()
118 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v1_0_enable_mgcg()
122 WREG32(VCE_CLOCK_GATING_A, tmp); in vce_v1_0_enable_mgcg()
127 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v1_0_enable_mgcg()
131 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v1_0_enable_mgcg()
141 WREG32(VCE_CLOCK_GATING_A, tmp); in vce_v1_0_init_cg()
146 WREG32(VCE_CLOCK_GATING_ in vce_v1_0_init_cg()
[all...]
H A Dr600.c126 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); in r600_rcu_rreg()
137 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); in r600_rcu_wreg()
138 WREG32(R600_RCU_DATA, (v)); in r600_rcu_wreg()
148 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); in r600_uvd_ctx_rreg()
159 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); in r600_uvd_ctx_wreg()
160 WREG32(R600_UVD_CTX_DATA, (v)); in r600_uvd_ctx_wreg()
346 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce3_program_fmt()
873 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_hpd_set_polarity()
881 WREG32(DC_HPD2_INT_CONTROL, tmp); in r600_hpd_set_polarity()
889 WREG32(DC_HPD3_INT_CONTRO in r600_hpd_set_polarity()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Drv515.c137 WREG32(R_000300_VGA_RENDER_CONTROL, in rv515_vga_render_disable()
202 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); in rv515_mc_rreg()
204 WREG32(MC_IND_INDEX, 0); in rv515_mc_rreg()
215 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); in rv515_mc_wreg()
216 WREG32(MC_IND_DATA, (v)); in rv515_mc_wreg()
217 WREG32(MC_IND_INDEX, 0); in rv515_mc_wreg()
277 WREG32(R_000300_VGA_RENDER_CONTROL, 0); in rv515_mc_stop()
286 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in rv515_mc_stop()
288 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); in rv515_mc_stop()
289 WREG32(AVIVO_D1CRTC_UPDATE_LOC in rv515_mc_stop()
[all...]
H A Dradeon_bios.c276 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); in ni_read_disabled_bios()
279 WREG32(AVIVO_D1VGA_CONTROL, in ni_read_disabled_bios()
282 WREG32(AVIVO_D2VGA_CONTROL, in ni_read_disabled_bios()
285 WREG32(AVIVO_VGA_RENDER_CONTROL, in ni_read_disabled_bios()
288 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); in ni_read_disabled_bios()
293 WREG32(R600_BUS_CNTL, bus_cntl); in ni_read_disabled_bios()
295 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); in ni_read_disabled_bios()
296 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); in ni_read_disabled_bios()
297 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); in ni_read_disabled_bios()
299 WREG32(R600_ROM_CNT in ni_read_disabled_bios()
[all...]
H A Dvce_v2_0.c46 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_sw_cg()
50 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
54 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
56 WREG32(VCE_CGTT_CLK_OVERRIDE, 0); in vce_v2_0_set_sw_cg()
61 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_sw_cg()
66 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
70 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
86 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_dyn_cg()
92 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_dyn_cg()
97 WREG32(VCE_UENC_REG_CLOCK_GATIN in vce_v2_0_set_dyn_cg()
[all...]
H A Duvd_v1_0.c70 WREG32(UVD_RBC_RB_WPTR, ring->wptr); in uvd_v1_0_set_wptr()
123 WREG32(UVD_VCPU_CACHE_OFFSET0, addr); in uvd_v1_0_resume()
124 WREG32(UVD_VCPU_CACHE_SIZE0, size); in uvd_v1_0_resume()
128 WREG32(UVD_VCPU_CACHE_OFFSET1, addr); in uvd_v1_0_resume()
129 WREG32(UVD_VCPU_CACHE_SIZE1, size); in uvd_v1_0_resume()
134 WREG32(UVD_VCPU_CACHE_OFFSET2, addr); in uvd_v1_0_resume()
135 WREG32(UVD_VCPU_CACHE_SIZE2, size); in uvd_v1_0_resume()
139 WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); in uvd_v1_0_resume()
143 WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); in uvd_v1_0_resume()
145 WREG32(UVD_FW_STAR in uvd_v1_0_resume()
[all...]
H A Dvce_v1_0.c98 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_set_wptr()
100 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_set_wptr()
110 WREG32(VCE_CLOCK_GATING_A, tmp); in vce_v1_0_enable_mgcg()
115 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v1_0_enable_mgcg()
119 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v1_0_enable_mgcg()
123 WREG32(VCE_CLOCK_GATING_A, tmp); in vce_v1_0_enable_mgcg()
128 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v1_0_enable_mgcg()
132 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v1_0_enable_mgcg()
142 WREG32(VCE_CLOCK_GATING_A, tmp); in vce_v1_0_init_cg()
147 WREG32(VCE_CLOCK_GATING_ in vce_v1_0_init_cg()
[all...]
H A Dr600.c126 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); in r600_rcu_rreg()
137 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); in r600_rcu_wreg()
138 WREG32(R600_RCU_DATA, (v)); in r600_rcu_wreg()
148 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); in r600_uvd_ctx_rreg()
159 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); in r600_uvd_ctx_wreg()
160 WREG32(R600_UVD_CTX_DATA, (v)); in r600_uvd_ctx_wreg()
346 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce3_program_fmt()
873 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_hpd_set_polarity()
881 WREG32(DC_HPD2_INT_CONTROL, tmp); in r600_hpd_set_polarity()
889 WREG32(DC_HPD3_INT_CONTRO in r600_hpd_set_polarity()
[all...]
/kernel/linux/linux-5.10/drivers/misc/habanalabs/gaudi/
H A Dgaudi_coresight.c406 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); in gaudi_config_stm()
414 WREG32(base_reg + 0xE80, 0x80004); in gaudi_config_stm()
415 WREG32(base_reg + 0xD64, 7); in gaudi_config_stm()
416 WREG32(base_reg + 0xD60, 0); in gaudi_config_stm()
417 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); in gaudi_config_stm()
418 WREG32(base_reg + 0xD60, 1); in gaudi_config_stm()
419 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask)); in gaudi_config_stm()
420 WREG32(base_reg + 0xE70, 0x10); in gaudi_config_stm()
421 WREG32(base_reg + 0xE60, 0); in gaudi_config_stm()
422 WREG32(base_re in gaudi_config_stm()
[all...]
H A Dgaudi.c812 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, GAUDI_EVENT_INTS_REGISTER); in gaudi_late_init()
1267 WREG32(mmNIF_RTR_CTRL_0_SCRAM_SRAM_EN, in gaudi_init_scrambler_sram()
1269 WREG32(mmNIF_RTR_CTRL_1_SCRAM_SRAM_EN, in gaudi_init_scrambler_sram()
1271 WREG32(mmNIF_RTR_CTRL_2_SCRAM_SRAM_EN, in gaudi_init_scrambler_sram()
1273 WREG32(mmNIF_RTR_CTRL_3_SCRAM_SRAM_EN, in gaudi_init_scrambler_sram()
1275 WREG32(mmNIF_RTR_CTRL_4_SCRAM_SRAM_EN, in gaudi_init_scrambler_sram()
1277 WREG32(mmNIF_RTR_CTRL_5_SCRAM_SRAM_EN, in gaudi_init_scrambler_sram()
1279 WREG32(mmNIF_RTR_CTRL_6_SCRAM_SRAM_EN, in gaudi_init_scrambler_sram()
1281 WREG32(mmNIF_RTR_CTRL_7_SCRAM_SRAM_EN, in gaudi_init_scrambler_sram()
1284 WREG32(mmSIF_RTR_CTRL_0_SCRAM_SRAM_E in gaudi_init_scrambler_sram()
[all...]
/kernel/linux/linux-6.6/drivers/accel/habanalabs/gaudi/
H A Dgaudi_coresight.c405 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); in gaudi_config_stm()
413 WREG32(base_reg + 0xE80, 0x80004); in gaudi_config_stm()
414 WREG32(base_reg + 0xD64, 7); in gaudi_config_stm()
415 WREG32(base_reg + 0xD60, 0); in gaudi_config_stm()
416 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); in gaudi_config_stm()
417 WREG32(base_reg + 0xD60, 1); in gaudi_config_stm()
418 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask)); in gaudi_config_stm()
419 WREG32(base_reg + 0xE70, 0x10); in gaudi_config_stm()
420 WREG32(base_reg + 0xE60, 0); in gaudi_config_stm()
421 WREG32(base_re in gaudi_config_stm()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dgmc_v6_0.c73 WREG32(mmBIF_FB_EN, 0); in gmc_v6_0_mc_stop()
77 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); in gmc_v6_0_mc_stop()
91 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); in gmc_v6_0_mc_resume()
95 WREG32(mmBIF_FB_EN, tmp); in gmc_v6_0_mc_resume()
179 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v6_0_mc_load_microcode()
180 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v6_0_mc_load_microcode()
184 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); in gmc_v6_0_mc_load_microcode()
185 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); in gmc_v6_0_mc_load_microcode()
189 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); in gmc_v6_0_mc_load_microcode()
193 WREG32(mmMC_SEQ_SUP_CNT in gmc_v6_0_mc_load_microcode()
[all...]
H A Dvce_v3_0.c85 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); in vce_v3_0_ring_get_rptr()
87 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); in vce_v3_0_ring_get_rptr()
96 WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); in vce_v3_0_ring_get_rptr()
117 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); in vce_v3_0_ring_get_wptr()
119 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); in vce_v3_0_ring_get_wptr()
128 WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); in vce_v3_0_ring_get_wptr()
148 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); in vce_v3_0_ring_set_wptr()
150 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); in vce_v3_0_ring_set_wptr()
153 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v3_0_ring_set_wptr()
155 WREG32(mmVCE_RB_WPTR in vce_v3_0_ring_set_wptr()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dgmc_v6_0.c73 WREG32(mmBIF_FB_EN, 0); in gmc_v6_0_mc_stop()
77 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); in gmc_v6_0_mc_stop()
91 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); in gmc_v6_0_mc_resume()
95 WREG32(mmBIF_FB_EN, tmp); in gmc_v6_0_mc_resume()
173 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v6_0_mc_load_microcode()
174 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v6_0_mc_load_microcode()
178 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); in gmc_v6_0_mc_load_microcode()
179 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); in gmc_v6_0_mc_load_microcode()
183 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); in gmc_v6_0_mc_load_microcode()
186 WREG32(mmMC_SEQ_SUP_CNT in gmc_v6_0_mc_load_microcode()
[all...]
H A Dvce_v3_0.c85 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); in vce_v3_0_ring_get_rptr()
87 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); in vce_v3_0_ring_get_rptr()
96 WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); in vce_v3_0_ring_get_rptr()
117 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); in vce_v3_0_ring_get_wptr()
119 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); in vce_v3_0_ring_get_wptr()
128 WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); in vce_v3_0_ring_get_wptr()
148 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); in vce_v3_0_ring_set_wptr()
150 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); in vce_v3_0_ring_set_wptr()
153 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v3_0_ring_set_wptr()
155 WREG32(mmVCE_RB_WPTR in vce_v3_0_ring_set_wptr()
[all...]

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