Lines Matching refs:WREG32
734 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_FULLY_TRUSTED);
736 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_PARTLY_TRUSTED);
895 WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size));
1106 WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address));
1107 WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address));
1109 WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH));
1110 WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0);
1111 WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0);
1113 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1114 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1115 WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1116 WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1117 WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1118 WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1119 WREG32(mmDMA_QM_0_GLBL_ERR_WDATA + reg_off,
1123 WREG32(mmDMA_QM_0_PQ_CFG1 + reg_off, 0x00020002);
1124 WREG32(mmDMA_QM_0_CQ_CFG1 + reg_off, 0x00080008);
1127 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_PARTLY_TRUSTED);
1129 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_FULLY_TRUSTED);
1134 WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, dma_err_cfg);
1135 WREG32(mmDMA_QM_0_GLBL_CFG0 + reg_off, QMAN_DMA_ENABLE);
1149 WREG32(mmDMA_CH_0_ERRMSG_ADDR_LO + reg_off, gic_base_lo);
1150 WREG32(mmDMA_CH_0_ERRMSG_ADDR_HI + reg_off, gic_base_hi);
1151 WREG32(mmDMA_CH_0_ERRMSG_WDATA + reg_off,
1160 WREG32(mmDMA_CH_0_WR_COMP_ADDR_HI + reg_off, upper_32_bits(sob_addr));
1161 WREG32(mmDMA_CH_0_WR_COMP_WDATA + reg_off, 0x80000001);
1205 WREG32(mmDMA_QM_0_GLBL_CFG0, 0);
1206 WREG32(mmDMA_QM_1_GLBL_CFG0, 0);
1207 WREG32(mmDMA_QM_2_GLBL_CFG0, 0);
1208 WREG32(mmDMA_QM_3_GLBL_CFG0, 0);
1209 WREG32(mmDMA_QM_4_GLBL_CFG0, 0);
1220 WREG32(cfg_reg, 1 << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
1349 WREG32(mmCPU_PQ_BASE_ADDR_LOW, lower_32_bits(cpu_pq->bus_address));
1350 WREG32(mmCPU_PQ_BASE_ADDR_HIGH, upper_32_bits(cpu_pq->bus_address));
1352 WREG32(mmCPU_EQ_BASE_ADDR_LOW, lower_32_bits(eq->bus_address));
1353 WREG32(mmCPU_EQ_BASE_ADDR_HIGH, upper_32_bits(eq->bus_address));
1355 WREG32(mmCPU_CQ_BASE_ADDR_LOW,
1357 WREG32(mmCPU_CQ_BASE_ADDR_HIGH,
1360 WREG32(mmCPU_PQ_LENGTH, HL_QUEUE_SIZE_IN_BYTES);
1361 WREG32(mmCPU_EQ_LENGTH, HL_EQ_SIZE_IN_BYTES);
1362 WREG32(mmCPU_CQ_LENGTH, HL_CPU_ACCESSIBLE_MEM_SIZE);
1365 WREG32(mmCPU_EQ_CI, 0);
1367 WREG32(mmCPU_IF_PF_PQ_PI, 0);
1369 WREG32(mmCPU_PQ_INIT_STATUS, PQ_INIT_STATUS_READY_FOR_CP);
1371 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
1401 WREG32(mmCPU_PLL_DIV_SEL_0, 0x0);
1402 WREG32(mmCPU_PLL_DIV_SEL_1, 0x0);
1403 WREG32(mmCPU_PLL_DIV_SEL_2, 0x0);
1404 WREG32(mmCPU_PLL_DIV_SEL_3, 0x0);
1406 WREG32(mmIC_PLL_DIV_SEL_0, 0x0);
1407 WREG32(mmIC_PLL_DIV_SEL_1, 0x0);
1408 WREG32(mmIC_PLL_DIV_SEL_2, 0x0);
1409 WREG32(mmIC_PLL_DIV_SEL_3, 0x0);
1411 WREG32(mmMC_PLL_DIV_SEL_0, 0x0);
1412 WREG32(mmMC_PLL_DIV_SEL_1, 0x0);
1413 WREG32(mmMC_PLL_DIV_SEL_2, 0x0);
1414 WREG32(mmMC_PLL_DIV_SEL_3, 0x0);
1416 WREG32(mmPSOC_MME_PLL_DIV_SEL_0, 0x0);
1417 WREG32(mmPSOC_MME_PLL_DIV_SEL_1, 0x0);
1418 WREG32(mmPSOC_MME_PLL_DIV_SEL_2, 0x0);
1419 WREG32(mmPSOC_MME_PLL_DIV_SEL_3, 0x0);
1421 WREG32(mmPSOC_PCI_PLL_DIV_SEL_0, 0x0);
1422 WREG32(mmPSOC_PCI_PLL_DIV_SEL_1, 0x0);
1423 WREG32(mmPSOC_PCI_PLL_DIV_SEL_2, 0x0);
1424 WREG32(mmPSOC_PCI_PLL_DIV_SEL_3, 0x0);
1426 WREG32(mmPSOC_EMMC_PLL_DIV_SEL_0, 0x0);
1427 WREG32(mmPSOC_EMMC_PLL_DIV_SEL_1, 0x0);
1428 WREG32(mmPSOC_EMMC_PLL_DIV_SEL_2, 0x0);
1429 WREG32(mmPSOC_EMMC_PLL_DIV_SEL_3, 0x0);
1431 WREG32(mmTPC_PLL_DIV_SEL_0, 0x0);
1432 WREG32(mmTPC_PLL_DIV_SEL_1, 0x0);
1433 WREG32(mmTPC_PLL_DIV_SEL_2, 0x0);
1434 WREG32(mmTPC_PLL_DIV_SEL_3, 0x0);
1439 WREG32(mmPSOC_MME_PLL_CLK_RLX_0, 0x100010);
1440 WREG32(mmIC_PLL_CLK_RLX_0, 0x100010);
1464 WREG32(mmTPC0_CFG_FUNC_MBIST_PAT + tpc_offset, val & 0xFFFFF000);
1466 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_0 + tpc_offset, 0x37FF);
1467 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_1 + tpc_offset, 0x303F);
1468 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_2 + tpc_offset, 0x71FF);
1469 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_3 + tpc_offset, 0x71FF);
1470 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_4 + tpc_offset, 0x70FF);
1471 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_5 + tpc_offset, 0x70FF);
1472 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_6 + tpc_offset, 0x70FF);
1473 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_7 + tpc_offset, 0x70FF);
1474 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_8 + tpc_offset, 0x70FF);
1475 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_9 + tpc_offset, 0x70FF);
1503 WREG32(tpc_slm_offset + (slm_index << 2), 0);
1559 WREG32(mmSRAM_Y0_X0_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1560 WREG32(mmSRAM_Y0_X1_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1561 WREG32(mmSRAM_Y0_X2_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1562 WREG32(mmSRAM_Y0_X3_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1563 WREG32(mmSRAM_Y0_X4_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1565 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_L_ARB + offset, 0x204);
1566 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_L_ARB + offset, 0x204);
1567 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_L_ARB + offset, 0x204);
1568 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_L_ARB + offset, 0x204);
1569 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_L_ARB + offset, 0x204);
1572 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_E_ARB + offset, 0x206);
1573 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_E_ARB + offset, 0x206);
1574 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_E_ARB + offset, 0x206);
1575 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_E_ARB + offset, 0x207);
1576 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_E_ARB + offset, 0x207);
1578 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_W_ARB + offset, 0x207);
1579 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_W_ARB + offset, 0x207);
1580 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_W_ARB + offset, 0x206);
1581 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_W_ARB + offset, 0x206);
1582 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_W_ARB + offset, 0x206);
1584 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_E_ARB + offset, 0x101);
1585 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_E_ARB + offset, 0x102);
1586 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_E_ARB + offset, 0x103);
1587 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_E_ARB + offset, 0x104);
1588 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_E_ARB + offset, 0x105);
1590 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_W_ARB + offset, 0x105);
1591 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_W_ARB + offset, 0x104);
1592 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_W_ARB + offset, 0x103);
1593 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_W_ARB + offset, 0x102);
1594 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_W_ARB + offset, 0x101);
1597 WREG32(mmMME_STORE_MAX_CREDIT, 0x21);
1598 WREG32(mmMME_AGU, 0x0f0f0f10);
1599 WREG32(mmMME_SEI_MASK, ~0x0);
1601 WREG32(mmMME6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1602 WREG32(mmMME5_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1603 WREG32(mmMME4_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1604 WREG32(mmMME3_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1605 WREG32(mmMME2_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1606 WREG32(mmMME1_RTR_HBW_RD_RQ_N_ARB, 0x07010701);
1607 WREG32(mmMME6_RTR_HBW_RD_RQ_S_ARB, 0x04010401);
1608 WREG32(mmMME5_RTR_HBW_RD_RQ_S_ARB, 0x04050401);
1609 WREG32(mmMME4_RTR_HBW_RD_RQ_S_ARB, 0x03070301);
1610 WREG32(mmMME3_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1611 WREG32(mmMME2_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1612 WREG32(mmMME1_RTR_HBW_RD_RQ_S_ARB, 0x01050105);
1613 WREG32(mmMME6_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1614 WREG32(mmMME5_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1615 WREG32(mmMME4_RTR_HBW_RD_RQ_W_ARB, 0x01040301);
1616 WREG32(mmMME3_RTR_HBW_RD_RQ_W_ARB, 0x01030401);
1617 WREG32(mmMME2_RTR_HBW_RD_RQ_W_ARB, 0x01040101);
1618 WREG32(mmMME1_RTR_HBW_RD_RQ_W_ARB, 0x01050101);
1619 WREG32(mmMME6_RTR_HBW_WR_RQ_N_ARB, 0x02020202);
1620 WREG32(mmMME5_RTR_HBW_WR_RQ_N_ARB, 0x01070101);
1621 WREG32(mmMME4_RTR_HBW_WR_RQ_N_ARB, 0x02020201);
1622 WREG32(mmMME3_RTR_HBW_WR_RQ_N_ARB, 0x07020701);
1623 WREG32(mmMME2_RTR_HBW_WR_RQ_N_ARB, 0x01020101);
1624 WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1625 WREG32(mmMME6_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1626 WREG32(mmMME5_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1627 WREG32(mmMME4_RTR_HBW_WR_RQ_S_ARB, 0x07020701);
1628 WREG32(mmMME3_RTR_HBW_WR_RQ_S_ARB, 0x02020201);
1629 WREG32(mmMME2_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1630 WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01020102);
1631 WREG32(mmMME6_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1632 WREG32(mmMME5_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1633 WREG32(mmMME4_RTR_HBW_WR_RQ_W_ARB, 0x07020707);
1634 WREG32(mmMME3_RTR_HBW_WR_RQ_W_ARB, 0x01020201);
1635 WREG32(mmMME2_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1636 WREG32(mmMME1_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1637 WREG32(mmMME6_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1638 WREG32(mmMME5_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1639 WREG32(mmMME4_RTR_HBW_RD_RS_N_ARB, 0x01060102);
1640 WREG32(mmMME3_RTR_HBW_RD_RS_N_ARB, 0x01040102);
1641 WREG32(mmMME2_RTR_HBW_RD_RS_N_ARB, 0x01020102);
1642 WREG32(mmMME1_RTR_HBW_RD_RS_N_ARB, 0x01020107);
1643 WREG32(mmMME6_RTR_HBW_RD_RS_S_ARB, 0x01020106);
1644 WREG32(mmMME5_RTR_HBW_RD_RS_S_ARB, 0x01020102);
1645 WREG32(mmMME4_RTR_HBW_RD_RS_S_ARB, 0x01040102);
1646 WREG32(mmMME3_RTR_HBW_RD_RS_S_ARB, 0x01060102);
1647 WREG32(mmMME2_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1648 WREG32(mmMME1_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1649 WREG32(mmMME6_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1650 WREG32(mmMME5_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1651 WREG32(mmMME4_RTR_HBW_RD_RS_E_ARB, 0x01040602);
1652 WREG32(mmMME3_RTR_HBW_RD_RS_E_ARB, 0x01060402);
1653 WREG32(mmMME2_RTR_HBW_RD_RS_E_ARB, 0x01070202);
1654 WREG32(mmMME1_RTR_HBW_RD_RS_E_ARB, 0x01070102);
1655 WREG32(mmMME6_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1656 WREG32(mmMME5_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1657 WREG32(mmMME4_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1658 WREG32(mmMME3_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1659 WREG32(mmMME2_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1660 WREG32(mmMME1_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1661 WREG32(mmMME6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1662 WREG32(mmMME5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1663 WREG32(mmMME4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1664 WREG32(mmMME3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1665 WREG32(mmMME2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1666 WREG32(mmMME1_RTR_HBW_WR_RS_N_ARB, 0x01010107);
1667 WREG32(mmMME6_RTR_HBW_WR_RS_S_ARB, 0x01010107);
1668 WREG32(mmMME5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1669 WREG32(mmMME4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1670 WREG32(mmMME3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1671 WREG32(mmMME2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1672 WREG32(mmMME1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1673 WREG32(mmMME6_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1674 WREG32(mmMME5_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1675 WREG32(mmMME4_RTR_HBW_WR_RS_E_ARB, 0x01040301);
1676 WREG32(mmMME3_RTR_HBW_WR_RS_E_ARB, 0x01030401);
1677 WREG32(mmMME2_RTR_HBW_WR_RS_E_ARB, 0x01040101);
1678 WREG32(mmMME1_RTR_HBW_WR_RS_E_ARB, 0x01050101);
1679 WREG32(mmMME6_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1680 WREG32(mmMME5_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1681 WREG32(mmMME4_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1682 WREG32(mmMME3_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1683 WREG32(mmMME2_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1684 WREG32(mmMME1_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1686 WREG32(mmTPC1_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1687 WREG32(mmTPC1_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1688 WREG32(mmTPC1_RTR_HBW_RD_RQ_E_ARB, 0x01060101);
1689 WREG32(mmTPC1_RTR_HBW_WR_RQ_N_ARB, 0x02020102);
1690 WREG32(mmTPC1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1691 WREG32(mmTPC1_RTR_HBW_WR_RQ_E_ARB, 0x02070202);
1692 WREG32(mmTPC1_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1693 WREG32(mmTPC1_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1694 WREG32(mmTPC1_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1695 WREG32(mmTPC1_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1696 WREG32(mmTPC1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1697 WREG32(mmTPC1_RTR_HBW_WR_RS_W_ARB, 0x01050101);
1699 WREG32(mmTPC2_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1700 WREG32(mmTPC2_RTR_HBW_RD_RQ_S_ARB, 0x01050101);
1701 WREG32(mmTPC2_RTR_HBW_RD_RQ_E_ARB, 0x01010201);
1702 WREG32(mmTPC2_RTR_HBW_WR_RQ_N_ARB, 0x02040102);
1703 WREG32(mmTPC2_RTR_HBW_WR_RQ_S_ARB, 0x01050101);
1704 WREG32(mmTPC2_RTR_HBW_WR_RQ_E_ARB, 0x02060202);
1705 WREG32(mmTPC2_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1706 WREG32(mmTPC2_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1707 WREG32(mmTPC2_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1708 WREG32(mmTPC2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1709 WREG32(mmTPC2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1710 WREG32(mmTPC2_RTR_HBW_WR_RS_W_ARB, 0x01040101);
1712 WREG32(mmTPC3_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1713 WREG32(mmTPC3_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1714 WREG32(mmTPC3_RTR_HBW_RD_RQ_E_ARB, 0x01040301);
1715 WREG32(mmTPC3_RTR_HBW_WR_RQ_N_ARB, 0x02060102);
1716 WREG32(mmTPC3_RTR_HBW_WR_RQ_S_ARB, 0x01040101);
1717 WREG32(mmTPC3_RTR_HBW_WR_RQ_E_ARB, 0x01040301);
1718 WREG32(mmTPC3_RTR_HBW_RD_RS_N_ARB, 0x01040201);
1719 WREG32(mmTPC3_RTR_HBW_RD_RS_S_ARB, 0x01060201);
1720 WREG32(mmTPC3_RTR_HBW_RD_RS_W_ARB, 0x01060402);
1721 WREG32(mmTPC3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1722 WREG32(mmTPC3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1723 WREG32(mmTPC3_RTR_HBW_WR_RS_W_ARB, 0x01030401);
1725 WREG32(mmTPC4_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1726 WREG32(mmTPC4_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1727 WREG32(mmTPC4_RTR_HBW_RD_RQ_E_ARB, 0x01030401);
1728 WREG32(mmTPC4_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1729 WREG32(mmTPC4_RTR_HBW_WR_RQ_S_ARB, 0x01030101);
1730 WREG32(mmTPC4_RTR_HBW_WR_RQ_E_ARB, 0x02060702);
1731 WREG32(mmTPC4_RTR_HBW_RD_RS_N_ARB, 0x01060201);
1732 WREG32(mmTPC4_RTR_HBW_RD_RS_S_ARB, 0x01040201);
1733 WREG32(mmTPC4_RTR_HBW_RD_RS_W_ARB, 0x01040602);
1734 WREG32(mmTPC4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1735 WREG32(mmTPC4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1736 WREG32(mmTPC4_RTR_HBW_WR_RS_W_ARB, 0x01040301);
1738 WREG32(mmTPC5_RTR_HBW_RD_RQ_N_ARB, 0x01050101);
1739 WREG32(mmTPC5_RTR_HBW_RD_RQ_S_ARB, 0x01020101);
1740 WREG32(mmTPC5_RTR_HBW_RD_RQ_E_ARB, 0x01200501);
1741 WREG32(mmTPC5_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1742 WREG32(mmTPC5_RTR_HBW_WR_RQ_S_ARB, 0x01020101);
1743 WREG32(mmTPC5_RTR_HBW_WR_RQ_E_ARB, 0x02020602);
1744 WREG32(mmTPC5_RTR_HBW_RD_RS_N_ARB, 0x01070201);
1745 WREG32(mmTPC5_RTR_HBW_RD_RS_S_ARB, 0x01020201);
1746 WREG32(mmTPC5_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1747 WREG32(mmTPC5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1748 WREG32(mmTPC5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1749 WREG32(mmTPC5_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1751 WREG32(mmTPC6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1752 WREG32(mmTPC6_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1753 WREG32(mmTPC6_RTR_HBW_RD_RQ_E_ARB, 0x01010601);
1754 WREG32(mmTPC6_RTR_HBW_WR_RQ_N_ARB, 0x01010101);
1755 WREG32(mmTPC6_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1756 WREG32(mmTPC6_RTR_HBW_WR_RQ_E_ARB, 0x02020702);
1757 WREG32(mmTPC6_RTR_HBW_RD_RS_N_ARB, 0x01010101);
1758 WREG32(mmTPC6_RTR_HBW_RD_RS_S_ARB, 0x01010101);
1759 WREG32(mmTPC6_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1760 WREG32(mmTPC6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1761 WREG32(mmTPC6_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1762 WREG32(mmTPC6_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1765 WREG32(mmMME1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1766 WREG32(mmMME2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1767 WREG32(mmMME3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1768 WREG32(mmMME4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1769 WREG32(mmMME5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1770 WREG32(mmMME6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1772 WREG32(mmTPC0_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1773 WREG32(mmTPC1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1774 WREG32(mmTPC2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1775 WREG32(mmTPC3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1776 WREG32(mmTPC4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1777 WREG32(mmTPC5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1778 WREG32(mmTPC6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1779 WREG32(mmTPC7_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1781 WREG32(mmPCI_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1782 WREG32(mmDMA_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1786 WREG32(mmMME1_RTR_SCRAMB_EN + offset,
1788 WREG32(mmMME1_RTR_NON_LIN_SCRAMB + offset,
1797 WREG32(mmTPC0_CFG_TPC_INTR_MASK + offset, tpc_intr_mask);
1799 WREG32(mmTPC0_NRTR_SCRAMB_EN + offset,
1801 WREG32(mmTPC0_NRTR_NON_LIN_SCRAMB + offset,
1808 WREG32(mmDMA_NRTR_SCRAMB_EN, 1 << DMA_NRTR_SCRAMB_EN_VAL_SHIFT);
1809 WREG32(mmDMA_NRTR_NON_LIN_SCRAMB,
1812 WREG32(mmPCI_NRTR_SCRAMB_EN, 1 << PCI_NRTR_SCRAMB_EN_VAL_SHIFT);
1813 WREG32(mmPCI_NRTR_NON_LIN_SCRAMB,
1823 WREG32(mmDMA_CH_1_CFG0, 0x0fff00F0);
1825 WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
1850 WREG32(mmMME_QM_PQ_BASE_LO, lower_32_bits(qman_base_addr));
1851 WREG32(mmMME_QM_PQ_BASE_HI, upper_32_bits(qman_base_addr));
1852 WREG32(mmMME_QM_PQ_SIZE, ilog2(MME_QMAN_LENGTH));
1853 WREG32(mmMME_QM_PQ_PI, 0);
1854 WREG32(mmMME_QM_PQ_CI, 0);
1855 WREG32(mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET, 0x10C0);
1856 WREG32(mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET, 0x10C4);
1857 WREG32(mmMME_QM_CP_LDMA_TSIZE_OFFSET, 0x10C8);
1858 WREG32(mmMME_QM_CP_LDMA_COMMIT_OFFSET, 0x10CC);
1860 WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1861 WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1862 WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1863 WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1866 WREG32(mmMME_QM_CQ_CFG1, 0x00080008);
1868 WREG32(mmMME_QM_GLBL_ERR_ADDR_LO, gic_base_lo);
1869 WREG32(mmMME_QM_GLBL_ERR_ADDR_HI, gic_base_hi);
1871 WREG32(mmMME_QM_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_QM);
1873 WREG32(mmMME_QM_GLBL_ERR_CFG, QMAN_MME_ERR_MSG_EN);
1875 WREG32(mmMME_QM_GLBL_PROT, QMAN_MME_ERR_PROT);
1877 WREG32(mmMME_QM_GLBL_CFG0, QMAN_MME_ENABLE);
1896 WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1897 WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1898 WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1899 WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1902 WREG32(mmMME_CMDQ_CQ_CFG1, 0x00140014);
1904 WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_LO, gic_base_lo);
1905 WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_HI, gic_base_hi);
1907 WREG32(mmMME_CMDQ_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_CMDQ);
1909 WREG32(mmMME_CMDQ_GLBL_ERR_CFG, CMDQ_MME_ERR_MSG_EN);
1911 WREG32(mmMME_CMDQ_GLBL_PROT, CMDQ_MME_ERR_PROT);
1913 WREG32(mmMME_CMDQ_GLBL_CFG0, CMDQ_MME_ENABLE);
1927 WREG32(mmMME_SM_BASE_ADDRESS_LOW, so_base_lo);
1928 WREG32(mmMME_SM_BASE_ADDRESS_HIGH, so_base_hi);
1956 WREG32(mmTPC0_QM_PQ_BASE_LO + reg_off, lower_32_bits(qman_base_addr));
1957 WREG32(mmTPC0_QM_PQ_BASE_HI + reg_off, upper_32_bits(qman_base_addr));
1958 WREG32(mmTPC0_QM_PQ_SIZE + reg_off, ilog2(TPC_QMAN_LENGTH));
1959 WREG32(mmTPC0_QM_PQ_PI + reg_off, 0);
1960 WREG32(mmTPC0_QM_PQ_CI + reg_off, 0);
1961 WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET + reg_off, 0x10C0);
1962 WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET + reg_off, 0x10C4);
1963 WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET + reg_off, 0x10C8);
1964 WREG32(mmTPC0_QM_CP_LDMA_COMMIT_OFFSET + reg_off, 0x10CC);
1966 WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1967 WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1968 WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1969 WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1971 WREG32(mmTPC0_QM_CQ_CFG1 + reg_off, 0x00080008);
1973 WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1974 WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1976 WREG32(mmTPC0_QM_GLBL_ERR_WDATA + reg_off,
1979 WREG32(mmTPC0_QM_GLBL_ERR_CFG + reg_off, QMAN_TPC_ERR_MSG_EN);
1981 WREG32(mmTPC0_QM_GLBL_PROT + reg_off, QMAN_TPC_ERR_PROT);
1983 WREG32(mmTPC0_QM_GLBL_CFG0 + reg_off, QMAN_TPC_ENABLE);
2003 WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
2004 WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
2005 WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
2006 WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
2008 WREG32(mmTPC0_CMDQ_CQ_CFG1 + reg_off, 0x00140014);
2010 WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
2011 WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
2013 WREG32(mmTPC0_CMDQ_GLBL_ERR_WDATA + reg_off,
2016 WREG32(mmTPC0_CMDQ_GLBL_ERR_CFG + reg_off, CMDQ_TPC_ERR_MSG_EN);
2018 WREG32(mmTPC0_CMDQ_GLBL_PROT + reg_off, CMDQ_TPC_ERR_PROT);
2020 WREG32(mmTPC0_CMDQ_GLBL_CFG0 + reg_off, CMDQ_TPC_ENABLE);
2038 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_LOW + i * cfg_off,
2040 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_HIGH + i * cfg_off,
2072 WREG32(mmMME_QM_GLBL_CFG0, 0);
2073 WREG32(mmMME_CMDQ_GLBL_CFG0, 0);
2079 WREG32(mmTPC0_QM_GLBL_CFG0, 0);
2080 WREG32(mmTPC0_CMDQ_GLBL_CFG0, 0);
2082 WREG32(mmTPC1_QM_GLBL_CFG0, 0);
2083 WREG32(mmTPC1_CMDQ_GLBL_CFG0, 0);
2085 WREG32(mmTPC2_QM_GLBL_CFG0, 0);
2086 WREG32(mmTPC2_CMDQ_GLBL_CFG0, 0);
2088 WREG32(mmTPC3_QM_GLBL_CFG0, 0);
2089 WREG32(mmTPC3_CMDQ_GLBL_CFG0, 0);
2091 WREG32(mmTPC4_QM_GLBL_CFG0, 0);
2092 WREG32(mmTPC4_CMDQ_GLBL_CFG0, 0);
2094 WREG32(mmTPC5_QM_GLBL_CFG0, 0);
2095 WREG32(mmTPC5_CMDQ_GLBL_CFG0, 0);
2097 WREG32(mmTPC6_QM_GLBL_CFG0, 0);
2098 WREG32(mmTPC6_CMDQ_GLBL_CFG0, 0);
2100 WREG32(mmTPC7_QM_GLBL_CFG0, 0);
2101 WREG32(mmTPC7_CMDQ_GLBL_CFG0, 0);
2320 WREG32(mmDMA_QM_0_GLBL_CFG1, 1 << DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT);
2321 WREG32(mmDMA_QM_1_GLBL_CFG1, 1 << DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT);
2322 WREG32(mmDMA_QM_2_GLBL_CFG1, 1 << DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT);
2323 WREG32(mmDMA_QM_3_GLBL_CFG1, 1 << DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT);
2324 WREG32(mmDMA_QM_4_GLBL_CFG1, 1 << DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT);
2334 WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
2335 WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC1_CFG_TPC_STALL_V_SHIFT);
2336 WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC2_CFG_TPC_STALL_V_SHIFT);
2337 WREG32(mmTPC3_CFG_TPC_STALL, 1 << TPC3_CFG_TPC_STALL_V_SHIFT);
2338 WREG32(mmTPC4_CFG_TPC_STALL, 1 << TPC4_CFG_TPC_STALL_V_SHIFT);
2339 WREG32(mmTPC5_CFG_TPC_STALL, 1 << TPC5_CFG_TPC_STALL_V_SHIFT);
2340 WREG32(mmTPC6_CFG_TPC_STALL, 1 << TPC6_CFG_TPC_STALL_V_SHIFT);
2341 WREG32(mmTPC7_CFG_TPC_STALL, 1 << TPC7_CFG_TPC_STALL_V_SHIFT);
2351 WREG32(mmMME_STALL, 0xFFFFFFFF);
2445 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
2448 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0xC, 0);
2449 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0x8, 0);
2452 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 1);
2458 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
2646 WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT);
2647 WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT);
2648 WREG32(MMU_ASID_BUSY, 0x80000000 | asid);
2694 WREG32(mmSTLB_CACHE_INV_BASE_39_8,
2696 WREG32(mmSTLB_CACHE_INV_BASE_49_40, MMU_CACHE_MNG_ADDR >> 40);
2704 WREG32(mmMMU_MMU_ENABLE, 1);
2705 WREG32(mmMMU_SPI_MASK, 0xF);
2735 WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY);
2806 WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_GOTO_WFE);
2807 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2816 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, RESET_ALL);
2821 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, DMA_MME_TPC_RESET);
2843 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2849 WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START,
2852 WREG32(mmPSOC_GLOBAL_CONF_SW_BTM_FSM,
2974 WREG32(db_reg_offset, db_value);
2979 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
3617 dev_dbg(hdev->dev, "WREG32 packet details:\n");
3623 dev_err(hdev->dev, "WREG32 packet with illegal address 0x%x\n",
3642 dev_err(hdev->dev, "WREG32 packet with illegal value 0x%x\n",
4179 WREG32(mmCPU_EQ_CI, val);
4198 WREG32(mmSYNC_MNGR_SOB_OBJ_0 + i, 0);
4201 WREG32(mmSYNC_MNGR_MON_STATUS_0 + i, 0);
4437 WREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD, 0);
4442 WREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD, 0);
4447 WREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD, 0);
4452 WREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD, 0);
4474 WREG32(mmMMU_PAGE_ERROR_CAPTURE, 0);
4855 WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO, lower_32_bits(sob_addr));
4860 WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO + channel_off * dma_id,
4864 WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
4949 WREG32(mmCPU_IF_ARUSER_OVR_EN, 0x7FF);
4950 WREG32(mmCPU_IF_AWUSER_OVR_EN, 0x7FF);
4991 WREG32(mmCPU_IF_ARUSER_OVR_EN, 0);
4992 WREG32(mmCPU_IF_AWUSER_OVR_EN, 0);
5061 WREG32(mmSTLB_INV_ALL_START, 1);
5335 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,