1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 * Authors: Christian König <christian.koenig@amd.com>
26 */
27
28 #include <linux/firmware.h>
29
30 #include "radeon.h"
31 #include "radeon_asic.h"
32 #include "sid.h"
33
34 #define VCE_V1_0_FW_SIZE (256 * 1024)
35 #define VCE_V1_0_STACK_SIZE (64 * 1024)
36 #define VCE_V1_0_DATA_SIZE (7808 * (RADEON_MAX_VCE_HANDLES + 1))
37
38 struct vce_v1_0_fw_signature
39 {
40 int32_t off;
41 uint32_t len;
42 int32_t num;
43 struct {
44 uint32_t chip_id;
45 uint32_t keyselect;
46 uint32_t nonce[4];
47 uint32_t sigval[4];
48 } val[8];
49 };
50
51 /**
52 * vce_v1_0_get_rptr - get read pointer
53 *
54 * @rdev: radeon_device pointer
55 * @ring: radeon_ring pointer
56 *
57 * Returns the current hardware read pointer
58 */
vce_v1_0_get_rptr(struct radeon_device *rdev, struct radeon_ring *ring)59 uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev,
60 struct radeon_ring *ring)
61 {
62 if (ring->idx == TN_RING_TYPE_VCE1_INDEX)
63 return RREG32(VCE_RB_RPTR);
64 else
65 return RREG32(VCE_RB_RPTR2);
66 }
67
68 /**
69 * vce_v1_0_get_wptr - get write pointer
70 *
71 * @rdev: radeon_device pointer
72 * @ring: radeon_ring pointer
73 *
74 * Returns the current hardware write pointer
75 */
vce_v1_0_get_wptr(struct radeon_device *rdev, struct radeon_ring *ring)76 uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev,
77 struct radeon_ring *ring)
78 {
79 if (ring->idx == TN_RING_TYPE_VCE1_INDEX)
80 return RREG32(VCE_RB_WPTR);
81 else
82 return RREG32(VCE_RB_WPTR2);
83 }
84
85 /**
86 * vce_v1_0_set_wptr - set write pointer
87 *
88 * @rdev: radeon_device pointer
89 * @ring: radeon_ring pointer
90 *
91 * Commits the write pointer to the hardware
92 */
vce_v1_0_set_wptr(struct radeon_device *rdev, struct radeon_ring *ring)93 void vce_v1_0_set_wptr(struct radeon_device *rdev,
94 struct radeon_ring *ring)
95 {
96 if (ring->idx == TN_RING_TYPE_VCE1_INDEX)
97 WREG32(VCE_RB_WPTR, ring->wptr);
98 else
99 WREG32(VCE_RB_WPTR2, ring->wptr);
100 }
101
vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable)102 void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable)
103 {
104 u32 tmp;
105
106 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_VCE_MGCG)) {
107 tmp = RREG32(VCE_CLOCK_GATING_A);
108 tmp |= CGC_DYN_CLOCK_MODE;
109 WREG32(VCE_CLOCK_GATING_A, tmp);
110
111 tmp = RREG32(VCE_UENC_CLOCK_GATING);
112 tmp &= ~0x1ff000;
113 tmp |= 0xff800000;
114 WREG32(VCE_UENC_CLOCK_GATING, tmp);
115
116 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
117 tmp &= ~0x3ff;
118 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
119 } else {
120 tmp = RREG32(VCE_CLOCK_GATING_A);
121 tmp &= ~CGC_DYN_CLOCK_MODE;
122 WREG32(VCE_CLOCK_GATING_A, tmp);
123
124 tmp = RREG32(VCE_UENC_CLOCK_GATING);
125 tmp |= 0x1ff000;
126 tmp &= ~0xff800000;
127 WREG32(VCE_UENC_CLOCK_GATING, tmp);
128
129 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
130 tmp |= 0x3ff;
131 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
132 }
133 }
134
vce_v1_0_init_cg(struct radeon_device *rdev)135 static void vce_v1_0_init_cg(struct radeon_device *rdev)
136 {
137 u32 tmp;
138
139 tmp = RREG32(VCE_CLOCK_GATING_A);
140 tmp |= CGC_DYN_CLOCK_MODE;
141 WREG32(VCE_CLOCK_GATING_A, tmp);
142
143 tmp = RREG32(VCE_CLOCK_GATING_B);
144 tmp |= 0x1e;
145 tmp &= ~0xe100e1;
146 WREG32(VCE_CLOCK_GATING_B, tmp);
147
148 tmp = RREG32(VCE_UENC_CLOCK_GATING);
149 tmp &= ~0xff9ff000;
150 WREG32(VCE_UENC_CLOCK_GATING, tmp);
151
152 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
153 tmp &= ~0x3ff;
154 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
155 }
156
vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data)157 int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data)
158 {
159 struct vce_v1_0_fw_signature *sign = (void*)rdev->vce_fw->data;
160 uint32_t chip_id;
161 int i;
162
163 switch (rdev->family) {
164 case CHIP_TAHITI:
165 chip_id = 0x01000014;
166 break;
167 case CHIP_VERDE:
168 chip_id = 0x01000015;
169 break;
170 case CHIP_PITCAIRN:
171 chip_id = 0x01000016;
172 break;
173 case CHIP_ARUBA:
174 chip_id = 0x01000017;
175 break;
176 default:
177 return -EINVAL;
178 }
179
180 for (i = 0; i < le32_to_cpu(sign->num); ++i) {
181 if (le32_to_cpu(sign->val[i].chip_id) == chip_id)
182 break;
183 }
184
185 if (i == le32_to_cpu(sign->num))
186 return -EINVAL;
187
188 data += (256 - 64) / 4;
189 data[0] = sign->val[i].nonce[0];
190 data[1] = sign->val[i].nonce[1];
191 data[2] = sign->val[i].nonce[2];
192 data[3] = sign->val[i].nonce[3];
193 data[4] = cpu_to_le32(le32_to_cpu(sign->len) + 64);
194
195 memset(&data[5], 0, 44);
196 memcpy(&data[16], &sign[1], rdev->vce_fw->size - sizeof(*sign));
197
198 data += (le32_to_cpu(sign->len) + 64) / 4;
199 data[0] = sign->val[i].sigval[0];
200 data[1] = sign->val[i].sigval[1];
201 data[2] = sign->val[i].sigval[2];
202 data[3] = sign->val[i].sigval[3];
203
204 rdev->vce.keyselect = le32_to_cpu(sign->val[i].keyselect);
205
206 return 0;
207 }
208
vce_v1_0_bo_size(struct radeon_device *rdev)209 unsigned vce_v1_0_bo_size(struct radeon_device *rdev)
210 {
211 WARN_ON(VCE_V1_0_FW_SIZE < rdev->vce_fw->size);
212 return VCE_V1_0_FW_SIZE + VCE_V1_0_STACK_SIZE + VCE_V1_0_DATA_SIZE;
213 }
214
vce_v1_0_resume(struct radeon_device *rdev)215 int vce_v1_0_resume(struct radeon_device *rdev)
216 {
217 uint64_t addr = rdev->vce.gpu_addr;
218 uint32_t size;
219 int i;
220
221 WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16));
222 WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
223 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
224 WREG32(VCE_CLOCK_GATING_B, 0);
225
226 WREG32_P(VCE_LMI_FW_PERIODIC_CTRL, 0x4, ~0x4);
227
228 WREG32(VCE_LMI_CTRL, 0x00398000);
229 WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1);
230 WREG32(VCE_LMI_SWAP_CNTL, 0);
231 WREG32(VCE_LMI_SWAP_CNTL1, 0);
232 WREG32(VCE_LMI_VM_CTRL, 0);
233
234 WREG32(VCE_VCPU_SCRATCH7, RADEON_MAX_VCE_HANDLES);
235
236 addr += 256;
237 size = VCE_V1_0_FW_SIZE;
238 WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
239 WREG32(VCE_VCPU_CACHE_SIZE0, size);
240
241 addr += size;
242 size = VCE_V1_0_STACK_SIZE;
243 WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
244 WREG32(VCE_VCPU_CACHE_SIZE1, size);
245
246 addr += size;
247 size = VCE_V1_0_DATA_SIZE;
248 WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
249 WREG32(VCE_VCPU_CACHE_SIZE2, size);
250
251 WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100);
252
253 WREG32(VCE_LMI_FW_START_KEYSEL, rdev->vce.keyselect);
254
255 for (i = 0; i < 10; ++i) {
256 mdelay(10);
257 if (RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_DONE)
258 break;
259 }
260
261 if (i == 10)
262 return -ETIMEDOUT;
263
264 if (!(RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_PASS))
265 return -EINVAL;
266
267 for (i = 0; i < 10; ++i) {
268 mdelay(10);
269 if (!(RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_BUSY))
270 break;
271 }
272
273 if (i == 10)
274 return -ETIMEDOUT;
275
276 vce_v1_0_init_cg(rdev);
277
278 return 0;
279 }
280
281 /**
282 * vce_v1_0_start - start VCE block
283 *
284 * @rdev: radeon_device pointer
285 *
286 * Setup and start the VCE block
287 */
vce_v1_0_start(struct radeon_device *rdev)288 int vce_v1_0_start(struct radeon_device *rdev)
289 {
290 struct radeon_ring *ring;
291 int i, j, r;
292
293 /* set BUSY flag */
294 WREG32_P(VCE_STATUS, 1, ~1);
295
296 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
297 WREG32(VCE_RB_RPTR, ring->wptr);
298 WREG32(VCE_RB_WPTR, ring->wptr);
299 WREG32(VCE_RB_BASE_LO, ring->gpu_addr);
300 WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
301 WREG32(VCE_RB_SIZE, ring->ring_size / 4);
302
303 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
304 WREG32(VCE_RB_RPTR2, ring->wptr);
305 WREG32(VCE_RB_WPTR2, ring->wptr);
306 WREG32(VCE_RB_BASE_LO2, ring->gpu_addr);
307 WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
308 WREG32(VCE_RB_SIZE2, ring->ring_size / 4);
309
310 WREG32_P(VCE_VCPU_CNTL, VCE_CLK_EN, ~VCE_CLK_EN);
311
312 WREG32_P(VCE_SOFT_RESET,
313 VCE_ECPU_SOFT_RESET |
314 VCE_FME_SOFT_RESET, ~(
315 VCE_ECPU_SOFT_RESET |
316 VCE_FME_SOFT_RESET));
317
318 mdelay(100);
319
320 WREG32_P(VCE_SOFT_RESET, 0, ~(
321 VCE_ECPU_SOFT_RESET |
322 VCE_FME_SOFT_RESET));
323
324 for (i = 0; i < 10; ++i) {
325 uint32_t status;
326 for (j = 0; j < 100; ++j) {
327 status = RREG32(VCE_STATUS);
328 if (status & 2)
329 break;
330 mdelay(10);
331 }
332 r = 0;
333 if (status & 2)
334 break;
335
336 DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
337 WREG32_P(VCE_SOFT_RESET, VCE_ECPU_SOFT_RESET, ~VCE_ECPU_SOFT_RESET);
338 mdelay(10);
339 WREG32_P(VCE_SOFT_RESET, 0, ~VCE_ECPU_SOFT_RESET);
340 mdelay(10);
341 r = -1;
342 }
343
344 /* clear BUSY flag */
345 WREG32_P(VCE_STATUS, 0, ~1);
346
347 if (r) {
348 DRM_ERROR("VCE not responding, giving up!!!\n");
349 return r;
350 }
351
352 return 0;
353 }
354
vce_v1_0_init(struct radeon_device *rdev)355 int vce_v1_0_init(struct radeon_device *rdev)
356 {
357 struct radeon_ring *ring;
358 int r;
359
360 r = vce_v1_0_start(rdev);
361 if (r)
362 return r;
363
364 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
365 ring->ready = true;
366 r = radeon_ring_test(rdev, TN_RING_TYPE_VCE1_INDEX, ring);
367 if (r) {
368 ring->ready = false;
369 return r;
370 }
371
372 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
373 ring->ready = true;
374 r = radeon_ring_test(rdev, TN_RING_TYPE_VCE2_INDEX, ring);
375 if (r) {
376 ring->ready = false;
377 return r;
378 }
379
380 DRM_INFO("VCE initialized successfully.\n");
381
382 return 0;
383 }
384