Lines Matching refs:WREG32
276 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
279 WREG32(AVIVO_D1VGA_CONTROL,
282 WREG32(AVIVO_D2VGA_CONTROL,
285 WREG32(AVIVO_VGA_RENDER_CONTROL,
288 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
293 WREG32(R600_BUS_CNTL, bus_cntl);
295 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
296 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
297 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
299 WREG32(R600_ROM_CNTL, rom_cntl);
323 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
325 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
327 WREG32(AVIVO_D1VGA_CONTROL,
330 WREG32(AVIVO_D2VGA_CONTROL,
333 WREG32(AVIVO_VGA_RENDER_CONTROL,
340 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
348 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
350 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
356 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
363 WREG32(RADEON_VIPH_CONTROL, viph_control);
364 WREG32(R600_BUS_CNTL, bus_cntl);
365 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
366 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
367 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
368 WREG32(R600_ROM_CNTL, rom_cntl);
402 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
404 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
406 WREG32(AVIVO_D1VGA_CONTROL,
409 WREG32(AVIVO_D2VGA_CONTROL,
412 WREG32(AVIVO_VGA_RENDER_CONTROL,
415 WREG32(R600_ROM_CNTL,
420 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
421 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
423 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
425 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
427 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
429 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
434 WREG32(RADEON_VIPH_CONTROL, viph_control);
435 WREG32(R600_BUS_CNTL, bus_cntl);
436 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
437 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
438 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
439 WREG32(R600_ROM_CNTL, rom_cntl);
440 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
441 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
442 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
443 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
444 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
445 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
472 WREG32(RADEON_SEPROM_CNTL1,
475 WREG32(RADEON_GPIOPAD_A, 0);
476 WREG32(RADEON_GPIOPAD_EN, 0);
477 WREG32(RADEON_GPIOPAD_MASK, 0);
480 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
483 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
486 WREG32(AVIVO_D1VGA_CONTROL,
489 WREG32(AVIVO_D2VGA_CONTROL,
492 WREG32(AVIVO_VGA_RENDER_CONTROL,
498 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
499 WREG32(RADEON_VIPH_CONTROL, viph_control);
500 WREG32(RV370_BUS_CNTL, bus_cntl);
501 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
502 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
503 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
504 WREG32(RADEON_GPIOPAD_A, gpiopad_a);
505 WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
506 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
540 WREG32(RADEON_SEPROM_CNTL1,
545 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
549 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
551 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
554 WREG32(RADEON_CRTC_GEN_CNTL,
559 WREG32(RADEON_CRTC2_GEN_CNTL,
564 WREG32(RADEON_CRTC_EXT_CNTL,
570 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
576 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
577 WREG32(RADEON_VIPH_CONTROL, viph_control);
579 WREG32(RV370_BUS_CNTL, bus_cntl);
581 WREG32(RADEON_BUS_CNTL, bus_cntl);
582 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
584 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
586 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
588 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);