Lines Matching refs:WREG32
126 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
137 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
138 WREG32(R600_RCU_DATA, (v));
148 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
159 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
160 WREG32(R600_UVD_CTX_DATA, (v));
346 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
873 WREG32(DC_HPD1_INT_CONTROL, tmp);
881 WREG32(DC_HPD2_INT_CONTROL, tmp);
889 WREG32(DC_HPD3_INT_CONTROL, tmp);
897 WREG32(DC_HPD4_INT_CONTROL, tmp);
905 WREG32(DC_HPD5_INT_CONTROL, tmp);
914 WREG32(DC_HPD6_INT_CONTROL, tmp);
927 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
935 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
943 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
975 WREG32(DC_HPD1_CONTROL, tmp);
978 WREG32(DC_HPD2_CONTROL, tmp);
981 WREG32(DC_HPD3_CONTROL, tmp);
984 WREG32(DC_HPD4_CONTROL, tmp);
988 WREG32(DC_HPD5_CONTROL, tmp);
991 WREG32(DC_HPD6_CONTROL, tmp);
999 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
1002 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
1005 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
1029 WREG32(DC_HPD1_CONTROL, 0);
1032 WREG32(DC_HPD2_CONTROL, 0);
1035 WREG32(DC_HPD3_CONTROL, 0);
1038 WREG32(DC_HPD4_CONTROL, 0);
1042 WREG32(DC_HPD5_CONTROL, 0);
1045 WREG32(DC_HPD6_CONTROL, 0);
1053 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
1056 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
1059 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
1090 WREG32(HDP_DEBUG1, 0);
1093 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1095 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
1096 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
1097 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
1143 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1146 WREG32(VM_L2_CNTL2, 0);
1147 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1153 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1154 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1155 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1156 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1157 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1158 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1159 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1160 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1161 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1162 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1163 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1164 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1165 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
1166 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
1167 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1168 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1169 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1170 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1171 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1172 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1174 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1177 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1194 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1197 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1199 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1203 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1204 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1205 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1206 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1207 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1208 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1209 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1210 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1211 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1212 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1213 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1214 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1215 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1216 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1217 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
1218 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
1235 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1238 WREG32(VM_L2_CNTL2, 0);
1239 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1245 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1246 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1247 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1248 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1249 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1250 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1251 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1252 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1253 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1254 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1255 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1256 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1257 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1258 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1260 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1284 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
1286 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
1296 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
1298 WREG32(R_0028FC_MC_DATA, v);
1299 WREG32(R_0028F8_MC_INDEX, 0x7F);
1311 WREG32((0x2c14 + j), 0x00000000);
1312 WREG32((0x2c18 + j), 0x00000000);
1313 WREG32((0x2c1c + j), 0x00000000);
1314 WREG32((0x2c20 + j), 0x00000000);
1315 WREG32((0x2c24 + j), 0x00000000);
1317 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1324 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1329 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1331 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1335 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1337 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1341 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1342 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1344 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1347 WREG32(MC_VM_FB_LOCATION, tmp);
1348 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1349 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1350 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1352 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1353 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1354 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1356 WREG32(MC_VM_AGP_BASE, 0);
1357 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1358 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1564 WREG32(R600_BIOS_3_SCRATCH, tmp);
1700 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1702 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1705 WREG32(RLC_CNTL, 0);
1711 WREG32(DMA_RB_CNTL, tmp);
1788 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1794 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1802 WREG32(SRBM_SOFT_RESET, tmp);
1808 WREG32(SRBM_SOFT_RESET, tmp);
1832 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1834 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1837 WREG32(RLC_CNTL, 0);
1842 WREG32(DMA_RB_CNTL, tmp);
1860 WREG32(BUS_CNTL, tmp);
1870 WREG32(SRBM_SOFT_RESET, tmp);
1872 WREG32(SRBM_SOFT_RESET, 0);
2077 WREG32((0x2c14 + j), 0x00000000);
2078 WREG32((0x2c18 + j), 0x00000000);
2079 WREG32((0x2c1c + j), 0x00000000);
2080 WREG32((0x2c20 + j), 0x00000000);
2081 WREG32((0x2c24 + j), 0x00000000);
2084 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
2141 WREG32(GB_TILING_CONFIG, tiling_config);
2142 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
2143 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
2144 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
2147 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
2148 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
2151 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
2152 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
2154 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
2158 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
2164 WREG32(SX_DEBUG_1, tmp);
2172 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
2174 WREG32(DB_DEBUG, 0);
2176 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
2179 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2180 WREG32(VGT_NUM_INSTANCES, 0);
2182 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
2183 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
2199 WREG32(SQ_MS_FIFO_SIZES, tmp);
2281 WREG32(SQ_CONFIG, sq_config);
2282 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2283 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2284 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2285 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2286 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2292 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
2294 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
2298 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
2300 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
2304 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
2308 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
2313 WREG32(VGT_STRMOUT_EN, 0);
2331 WREG32(VGT_ES_PER_GS, 128);
2332 WREG32(VGT_GS_PER_ES, tmp);
2333 WREG32(VGT_GS_PER_VS, 2);
2334 WREG32(VGT_GS_VERTEX_REUSE, 16);
2337 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2338 WREG32(VGT_STRMOUT_EN, 0);
2339 WREG32(SX_MISC, 0);
2340 WREG32(PA_SC_MODE_CNTL, 0);
2341 WREG32(PA_SC_AA_CONFIG, 0);
2342 WREG32(PA_SC_LINE_STIPPLE, 0);
2343 WREG32(SPI_INPUT_Z, 0);
2344 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
2345 WREG32(CB_COLOR7_FRAG, 0);
2348 WREG32(CB_COLOR0_BASE, 0);
2349 WREG32(CB_COLOR1_BASE, 0);
2350 WREG32(CB_COLOR2_BASE, 0);
2351 WREG32(CB_COLOR3_BASE, 0);
2352 WREG32(CB_COLOR4_BASE, 0);
2353 WREG32(CB_COLOR5_BASE, 0);
2354 WREG32(CB_COLOR6_BASE, 0);
2355 WREG32(CB_COLOR7_BASE, 0);
2356 WREG32(CB_COLOR7_FRAG, 0);
2376 WREG32(TC_CNTL, tmp);
2379 WREG32(HDP_HOST_PATH_CNTL, tmp);
2383 WREG32(ARB_POP, tmp);
2385 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2386 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
2388 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
2389 WREG32(VC_ENHANCE, 0);
2402 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2414 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2416 WREG32(PCIE_PORT_DATA, (v));
2428 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
2429 WREG32(SCRATCH_UMSK, 0);
2639 WREG32(R600_CP_RB_WPTR, ring->wptr);
2653 WREG32(CP_RB_CNTL,
2660 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2663 WREG32(GRBM_SOFT_RESET, 0);
2665 WREG32(CP_ME_RAM_WADDR, 0);
2668 WREG32(CP_ME_RAM_WADDR, 0);
2670 WREG32(CP_ME_RAM_DATA,
2674 WREG32(CP_PFP_UCODE_ADDR, 0);
2676 WREG32(CP_PFP_UCODE_DATA,
2679 WREG32(CP_PFP_UCODE_ADDR, 0);
2680 WREG32(CP_ME_RAM_WADDR, 0);
2681 WREG32(CP_ME_RAM_RADDR, 0);
2711 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2723 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2726 WREG32(GRBM_SOFT_RESET, 0);
2734 WREG32(CP_RB_CNTL, tmp);
2735 WREG32(CP_SEM_WAIT_TIMER, 0x0);
2738 WREG32(CP_RB_WPTR_DELAY, 0);
2741 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2742 WREG32(CP_RB_RPTR_WR, 0);
2744 WREG32(CP_RB_WPTR, ring->wptr);
2747 WREG32(CP_RB_RPTR_ADDR,
2749 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2750 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2753 WREG32(SCRATCH_UMSK, 0xff);
2756 WREG32(SCRATCH_UMSK, 0);
2760 WREG32(CP_RB_CNTL, tmp);
2762 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2763 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2834 WREG32(scratch, 0xCAFEDEAD);
3200 WREG32(CONFIG_CNTL, temp);
3412 WREG32(scratch, 0xCAFEDEAD);
3539 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3542 WREG32(SRBM_SOFT_RESET, 0);
3546 WREG32(RLC_CNTL, 0);
3551 WREG32(RLC_CNTL, RLC_ENABLE);
3564 WREG32(RLC_HB_CNTL, 0);
3566 WREG32(RLC_HB_BASE, 0);
3567 WREG32(RLC_HB_RPTR, 0);
3568 WREG32(RLC_HB_WPTR, 0);
3569 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3570 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3571 WREG32(RLC_MC_CNTL, 0);
3572 WREG32(RLC_UCODE_CNTL, 0);
3577 WREG32(RLC_UCODE_ADDR, i);
3578 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3582 WREG32(RLC_UCODE_ADDR, i);
3583 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3586 WREG32(RLC_UCODE_ADDR, 0);
3600 WREG32(IH_CNTL, ih_cntl);
3601 WREG32(IH_RB_CNTL, ih_rb_cntl);
3612 WREG32(IH_RB_CNTL, ih_rb_cntl);
3613 WREG32(IH_CNTL, ih_cntl);
3615 WREG32(IH_RB_RPTR, 0);
3616 WREG32(IH_RB_WPTR, 0);
3625 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3627 WREG32(DMA_CNTL, tmp);
3628 WREG32(GRBM_INT_CNTL, 0);
3629 WREG32(DxMODE_INT_MASK, 0);
3630 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3631 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
3633 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3634 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3636 WREG32(DC_HPD1_INT_CONTROL, tmp);
3638 WREG32(DC_HPD2_INT_CONTROL, tmp);
3640 WREG32(DC_HPD3_INT_CONTROL, tmp);
3642 WREG32(DC_HPD4_INT_CONTROL, tmp);
3645 WREG32(DC_HPD5_INT_CONTROL, tmp);
3647 WREG32(DC_HPD6_INT_CONTROL, tmp);
3649 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3651 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3654 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3656 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3659 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3660 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3662 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3664 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3666 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3668 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3670 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3700 WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8);
3708 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3710 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3721 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3722 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3724 WREG32(IH_RB_CNTL, ih_rb_cntl);
3727 WREG32(IH_RB_RPTR, 0);
3728 WREG32(IH_RB_WPTR, 0);
3735 WREG32(IH_CNTL, ih_cntl);
3876 WREG32(CP_INT_CNTL, cp_int_cntl);
3877 WREG32(DMA_CNTL, dma_cntl);
3878 WREG32(DxMODE_INT_MASK, mode_int);
3879 WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3880 WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3881 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3883 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3884 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3885 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3886 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3888 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3889 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3890 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3891 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
3893 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3894 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3897 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3898 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3899 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3900 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3901 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3904 WREG32(CG_THERMAL_INT, thermal_int);
3906 WREG32(RV770_CG_THERMAL_INT, thermal_int);
3941 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3943 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3945 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3947 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3949 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3951 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3956 WREG32(DC_HPD1_INT_CONTROL, tmp);
3960 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3967 WREG32(DC_HPD2_INT_CONTROL, tmp);
3971 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3978 WREG32(DC_HPD3_INT_CONTROL, tmp);
3982 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3988 WREG32(DC_HPD4_INT_CONTROL, tmp);
3994 WREG32(DC_HPD5_INT_CONTROL, tmp);
3999 WREG32(DC_HPD6_INT_CONTROL, tmp);
4004 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
4009 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
4015 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
4021 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
4025 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
4060 WREG32(IH_RB_CNTL, tmp);
4325 WREG32(IH_RB_RPTR, rptr);
4334 WREG32(IH_RB_RPTR, rptr);
4396 WREG32(HDP_DEBUG1, 0);
4399 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
4555 WREG32(MM_CFGREGS_CNTL, 0x8);
4557 WREG32(MM_CFGREGS_CNTL, 0);
4571 WREG32(0x541c, tmp | 0x8);
4572 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4577 WREG32(MM_CFGREGS_CNTL, 0);
4619 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);