Lines Matching refs:WREG32
657 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_FULLY_TRUSTED);
659 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_PARTLY_TRUSTED);
747 WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size));
756 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
921 WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address));
922 WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address));
924 WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH));
925 WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0);
926 WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0);
928 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
929 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
930 WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
931 WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
932 WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
933 WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
934 WREG32(mmDMA_QM_0_GLBL_ERR_WDATA + reg_off,
938 WREG32(mmDMA_QM_0_PQ_CFG1 + reg_off, 0x00020002);
939 WREG32(mmDMA_QM_0_CQ_CFG1 + reg_off, 0x00080008);
942 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_PARTLY_TRUSTED);
944 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_FULLY_TRUSTED);
949 WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, dma_err_cfg);
950 WREG32(mmDMA_QM_0_GLBL_CFG0 + reg_off, QMAN_DMA_ENABLE);
964 WREG32(mmDMA_CH_0_ERRMSG_ADDR_LO + reg_off, gic_base_lo);
965 WREG32(mmDMA_CH_0_ERRMSG_ADDR_HI + reg_off, gic_base_hi);
966 WREG32(mmDMA_CH_0_ERRMSG_WDATA + reg_off,
975 WREG32(mmDMA_CH_0_WR_COMP_ADDR_HI + reg_off, upper_32_bits(sob_addr));
976 WREG32(mmDMA_CH_0_WR_COMP_WDATA + reg_off, 0x80000001);
1020 WREG32(mmDMA_QM_0_GLBL_CFG0, 0);
1021 WREG32(mmDMA_QM_1_GLBL_CFG0, 0);
1022 WREG32(mmDMA_QM_2_GLBL_CFG0, 0);
1023 WREG32(mmDMA_QM_3_GLBL_CFG0, 0);
1024 WREG32(mmDMA_QM_4_GLBL_CFG0, 0);
1035 WREG32(cfg_reg, 1 << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
1163 WREG32(mmCPU_PQ_BASE_ADDR_LOW, lower_32_bits(cpu_pq->bus_address));
1164 WREG32(mmCPU_PQ_BASE_ADDR_HIGH, upper_32_bits(cpu_pq->bus_address));
1166 WREG32(mmCPU_EQ_BASE_ADDR_LOW, lower_32_bits(eq->bus_address));
1167 WREG32(mmCPU_EQ_BASE_ADDR_HIGH, upper_32_bits(eq->bus_address));
1169 WREG32(mmCPU_CQ_BASE_ADDR_LOW,
1171 WREG32(mmCPU_CQ_BASE_ADDR_HIGH,
1174 WREG32(mmCPU_PQ_LENGTH, HL_QUEUE_SIZE_IN_BYTES);
1175 WREG32(mmCPU_EQ_LENGTH, HL_EQ_SIZE_IN_BYTES);
1176 WREG32(mmCPU_CQ_LENGTH, HL_CPU_ACCESSIBLE_MEM_SIZE);
1179 WREG32(mmCPU_EQ_CI, 0);
1181 WREG32(mmCPU_IF_PF_PQ_PI, 0);
1183 WREG32(mmCPU_PQ_INIT_STATUS, PQ_INIT_STATUS_READY_FOR_CP);
1185 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
1208 WREG32(mmCPU_PLL_DIV_SEL_0, 0x0);
1209 WREG32(mmCPU_PLL_DIV_SEL_1, 0x0);
1210 WREG32(mmCPU_PLL_DIV_SEL_2, 0x0);
1211 WREG32(mmCPU_PLL_DIV_SEL_3, 0x0);
1213 WREG32(mmIC_PLL_DIV_SEL_0, 0x0);
1214 WREG32(mmIC_PLL_DIV_SEL_1, 0x0);
1215 WREG32(mmIC_PLL_DIV_SEL_2, 0x0);
1216 WREG32(mmIC_PLL_DIV_SEL_3, 0x0);
1218 WREG32(mmMC_PLL_DIV_SEL_0, 0x0);
1219 WREG32(mmMC_PLL_DIV_SEL_1, 0x0);
1220 WREG32(mmMC_PLL_DIV_SEL_2, 0x0);
1221 WREG32(mmMC_PLL_DIV_SEL_3, 0x0);
1223 WREG32(mmPSOC_MME_PLL_DIV_SEL_0, 0x0);
1224 WREG32(mmPSOC_MME_PLL_DIV_SEL_1, 0x0);
1225 WREG32(mmPSOC_MME_PLL_DIV_SEL_2, 0x0);
1226 WREG32(mmPSOC_MME_PLL_DIV_SEL_3, 0x0);
1228 WREG32(mmPSOC_PCI_PLL_DIV_SEL_0, 0x0);
1229 WREG32(mmPSOC_PCI_PLL_DIV_SEL_1, 0x0);
1230 WREG32(mmPSOC_PCI_PLL_DIV_SEL_2, 0x0);
1231 WREG32(mmPSOC_PCI_PLL_DIV_SEL_3, 0x0);
1233 WREG32(mmPSOC_EMMC_PLL_DIV_SEL_0, 0x0);
1234 WREG32(mmPSOC_EMMC_PLL_DIV_SEL_1, 0x0);
1235 WREG32(mmPSOC_EMMC_PLL_DIV_SEL_2, 0x0);
1236 WREG32(mmPSOC_EMMC_PLL_DIV_SEL_3, 0x0);
1238 WREG32(mmTPC_PLL_DIV_SEL_0, 0x0);
1239 WREG32(mmTPC_PLL_DIV_SEL_1, 0x0);
1240 WREG32(mmTPC_PLL_DIV_SEL_2, 0x0);
1241 WREG32(mmTPC_PLL_DIV_SEL_3, 0x0);
1246 WREG32(mmPSOC_MME_PLL_CLK_RLX_0, 0x100010);
1247 WREG32(mmIC_PLL_CLK_RLX_0, 0x100010);
1271 WREG32(mmTPC0_CFG_FUNC_MBIST_PAT + tpc_offset, val & 0xFFFFF000);
1273 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_0 + tpc_offset, 0x37FF);
1274 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_1 + tpc_offset, 0x303F);
1275 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_2 + tpc_offset, 0x71FF);
1276 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_3 + tpc_offset, 0x71FF);
1277 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_4 + tpc_offset, 0x70FF);
1278 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_5 + tpc_offset, 0x70FF);
1279 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_6 + tpc_offset, 0x70FF);
1280 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_7 + tpc_offset, 0x70FF);
1281 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_8 + tpc_offset, 0x70FF);
1282 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_9 + tpc_offset, 0x70FF);
1310 WREG32(tpc_slm_offset + (slm_index << 2), 0);
1366 WREG32(mmSRAM_Y0_X0_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1367 WREG32(mmSRAM_Y0_X1_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1368 WREG32(mmSRAM_Y0_X2_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1369 WREG32(mmSRAM_Y0_X3_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1370 WREG32(mmSRAM_Y0_X4_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1372 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_L_ARB + offset, 0x204);
1373 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_L_ARB + offset, 0x204);
1374 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_L_ARB + offset, 0x204);
1375 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_L_ARB + offset, 0x204);
1376 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_L_ARB + offset, 0x204);
1379 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_E_ARB + offset, 0x206);
1380 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_E_ARB + offset, 0x206);
1381 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_E_ARB + offset, 0x206);
1382 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_E_ARB + offset, 0x207);
1383 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_E_ARB + offset, 0x207);
1385 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_W_ARB + offset, 0x207);
1386 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_W_ARB + offset, 0x207);
1387 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_W_ARB + offset, 0x206);
1388 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_W_ARB + offset, 0x206);
1389 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_W_ARB + offset, 0x206);
1391 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_E_ARB + offset, 0x101);
1392 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_E_ARB + offset, 0x102);
1393 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_E_ARB + offset, 0x103);
1394 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_E_ARB + offset, 0x104);
1395 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_E_ARB + offset, 0x105);
1397 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_W_ARB + offset, 0x105);
1398 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_W_ARB + offset, 0x104);
1399 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_W_ARB + offset, 0x103);
1400 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_W_ARB + offset, 0x102);
1401 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_W_ARB + offset, 0x101);
1404 WREG32(mmMME_STORE_MAX_CREDIT, 0x21);
1405 WREG32(mmMME_AGU, 0x0f0f0f10);
1406 WREG32(mmMME_SEI_MASK, ~0x0);
1408 WREG32(mmMME6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1409 WREG32(mmMME5_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1410 WREG32(mmMME4_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1411 WREG32(mmMME3_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1412 WREG32(mmMME2_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1413 WREG32(mmMME1_RTR_HBW_RD_RQ_N_ARB, 0x07010701);
1414 WREG32(mmMME6_RTR_HBW_RD_RQ_S_ARB, 0x04010401);
1415 WREG32(mmMME5_RTR_HBW_RD_RQ_S_ARB, 0x04050401);
1416 WREG32(mmMME4_RTR_HBW_RD_RQ_S_ARB, 0x03070301);
1417 WREG32(mmMME3_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1418 WREG32(mmMME2_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1419 WREG32(mmMME1_RTR_HBW_RD_RQ_S_ARB, 0x01050105);
1420 WREG32(mmMME6_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1421 WREG32(mmMME5_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1422 WREG32(mmMME4_RTR_HBW_RD_RQ_W_ARB, 0x01040301);
1423 WREG32(mmMME3_RTR_HBW_RD_RQ_W_ARB, 0x01030401);
1424 WREG32(mmMME2_RTR_HBW_RD_RQ_W_ARB, 0x01040101);
1425 WREG32(mmMME1_RTR_HBW_RD_RQ_W_ARB, 0x01050101);
1426 WREG32(mmMME6_RTR_HBW_WR_RQ_N_ARB, 0x02020202);
1427 WREG32(mmMME5_RTR_HBW_WR_RQ_N_ARB, 0x01070101);
1428 WREG32(mmMME4_RTR_HBW_WR_RQ_N_ARB, 0x02020201);
1429 WREG32(mmMME3_RTR_HBW_WR_RQ_N_ARB, 0x07020701);
1430 WREG32(mmMME2_RTR_HBW_WR_RQ_N_ARB, 0x01020101);
1431 WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1432 WREG32(mmMME6_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1433 WREG32(mmMME5_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1434 WREG32(mmMME4_RTR_HBW_WR_RQ_S_ARB, 0x07020701);
1435 WREG32(mmMME3_RTR_HBW_WR_RQ_S_ARB, 0x02020201);
1436 WREG32(mmMME2_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1437 WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01020102);
1438 WREG32(mmMME6_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1439 WREG32(mmMME5_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1440 WREG32(mmMME4_RTR_HBW_WR_RQ_W_ARB, 0x07020707);
1441 WREG32(mmMME3_RTR_HBW_WR_RQ_W_ARB, 0x01020201);
1442 WREG32(mmMME2_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1443 WREG32(mmMME1_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1444 WREG32(mmMME6_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1445 WREG32(mmMME5_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1446 WREG32(mmMME4_RTR_HBW_RD_RS_N_ARB, 0x01060102);
1447 WREG32(mmMME3_RTR_HBW_RD_RS_N_ARB, 0x01040102);
1448 WREG32(mmMME2_RTR_HBW_RD_RS_N_ARB, 0x01020102);
1449 WREG32(mmMME1_RTR_HBW_RD_RS_N_ARB, 0x01020107);
1450 WREG32(mmMME6_RTR_HBW_RD_RS_S_ARB, 0x01020106);
1451 WREG32(mmMME5_RTR_HBW_RD_RS_S_ARB, 0x01020102);
1452 WREG32(mmMME4_RTR_HBW_RD_RS_S_ARB, 0x01040102);
1453 WREG32(mmMME3_RTR_HBW_RD_RS_S_ARB, 0x01060102);
1454 WREG32(mmMME2_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1455 WREG32(mmMME1_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1456 WREG32(mmMME6_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1457 WREG32(mmMME5_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1458 WREG32(mmMME4_RTR_HBW_RD_RS_E_ARB, 0x01040602);
1459 WREG32(mmMME3_RTR_HBW_RD_RS_E_ARB, 0x01060402);
1460 WREG32(mmMME2_RTR_HBW_RD_RS_E_ARB, 0x01070202);
1461 WREG32(mmMME1_RTR_HBW_RD_RS_E_ARB, 0x01070102);
1462 WREG32(mmMME6_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1463 WREG32(mmMME5_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1464 WREG32(mmMME4_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1465 WREG32(mmMME3_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1466 WREG32(mmMME2_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1467 WREG32(mmMME1_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1468 WREG32(mmMME6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1469 WREG32(mmMME5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1470 WREG32(mmMME4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1471 WREG32(mmMME3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1472 WREG32(mmMME2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1473 WREG32(mmMME1_RTR_HBW_WR_RS_N_ARB, 0x01010107);
1474 WREG32(mmMME6_RTR_HBW_WR_RS_S_ARB, 0x01010107);
1475 WREG32(mmMME5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1476 WREG32(mmMME4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1477 WREG32(mmMME3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1478 WREG32(mmMME2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1479 WREG32(mmMME1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1480 WREG32(mmMME6_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1481 WREG32(mmMME5_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1482 WREG32(mmMME4_RTR_HBW_WR_RS_E_ARB, 0x01040301);
1483 WREG32(mmMME3_RTR_HBW_WR_RS_E_ARB, 0x01030401);
1484 WREG32(mmMME2_RTR_HBW_WR_RS_E_ARB, 0x01040101);
1485 WREG32(mmMME1_RTR_HBW_WR_RS_E_ARB, 0x01050101);
1486 WREG32(mmMME6_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1487 WREG32(mmMME5_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1488 WREG32(mmMME4_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1489 WREG32(mmMME3_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1490 WREG32(mmMME2_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1491 WREG32(mmMME1_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1493 WREG32(mmTPC1_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1494 WREG32(mmTPC1_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1495 WREG32(mmTPC1_RTR_HBW_RD_RQ_E_ARB, 0x01060101);
1496 WREG32(mmTPC1_RTR_HBW_WR_RQ_N_ARB, 0x02020102);
1497 WREG32(mmTPC1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1498 WREG32(mmTPC1_RTR_HBW_WR_RQ_E_ARB, 0x02070202);
1499 WREG32(mmTPC1_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1500 WREG32(mmTPC1_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1501 WREG32(mmTPC1_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1502 WREG32(mmTPC1_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1503 WREG32(mmTPC1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1504 WREG32(mmTPC1_RTR_HBW_WR_RS_W_ARB, 0x01050101);
1506 WREG32(mmTPC2_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1507 WREG32(mmTPC2_RTR_HBW_RD_RQ_S_ARB, 0x01050101);
1508 WREG32(mmTPC2_RTR_HBW_RD_RQ_E_ARB, 0x01010201);
1509 WREG32(mmTPC2_RTR_HBW_WR_RQ_N_ARB, 0x02040102);
1510 WREG32(mmTPC2_RTR_HBW_WR_RQ_S_ARB, 0x01050101);
1511 WREG32(mmTPC2_RTR_HBW_WR_RQ_E_ARB, 0x02060202);
1512 WREG32(mmTPC2_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1513 WREG32(mmTPC2_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1514 WREG32(mmTPC2_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1515 WREG32(mmTPC2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1516 WREG32(mmTPC2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1517 WREG32(mmTPC2_RTR_HBW_WR_RS_W_ARB, 0x01040101);
1519 WREG32(mmTPC3_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1520 WREG32(mmTPC3_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1521 WREG32(mmTPC3_RTR_HBW_RD_RQ_E_ARB, 0x01040301);
1522 WREG32(mmTPC3_RTR_HBW_WR_RQ_N_ARB, 0x02060102);
1523 WREG32(mmTPC3_RTR_HBW_WR_RQ_S_ARB, 0x01040101);
1524 WREG32(mmTPC3_RTR_HBW_WR_RQ_E_ARB, 0x01040301);
1525 WREG32(mmTPC3_RTR_HBW_RD_RS_N_ARB, 0x01040201);
1526 WREG32(mmTPC3_RTR_HBW_RD_RS_S_ARB, 0x01060201);
1527 WREG32(mmTPC3_RTR_HBW_RD_RS_W_ARB, 0x01060402);
1528 WREG32(mmTPC3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1529 WREG32(mmTPC3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1530 WREG32(mmTPC3_RTR_HBW_WR_RS_W_ARB, 0x01030401);
1532 WREG32(mmTPC4_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1533 WREG32(mmTPC4_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1534 WREG32(mmTPC4_RTR_HBW_RD_RQ_E_ARB, 0x01030401);
1535 WREG32(mmTPC4_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1536 WREG32(mmTPC4_RTR_HBW_WR_RQ_S_ARB, 0x01030101);
1537 WREG32(mmTPC4_RTR_HBW_WR_RQ_E_ARB, 0x02060702);
1538 WREG32(mmTPC4_RTR_HBW_RD_RS_N_ARB, 0x01060201);
1539 WREG32(mmTPC4_RTR_HBW_RD_RS_S_ARB, 0x01040201);
1540 WREG32(mmTPC4_RTR_HBW_RD_RS_W_ARB, 0x01040602);
1541 WREG32(mmTPC4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1542 WREG32(mmTPC4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1543 WREG32(mmTPC4_RTR_HBW_WR_RS_W_ARB, 0x01040301);
1545 WREG32(mmTPC5_RTR_HBW_RD_RQ_N_ARB, 0x01050101);
1546 WREG32(mmTPC5_RTR_HBW_RD_RQ_S_ARB, 0x01020101);
1547 WREG32(mmTPC5_RTR_HBW_RD_RQ_E_ARB, 0x01200501);
1548 WREG32(mmTPC5_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1549 WREG32(mmTPC5_RTR_HBW_WR_RQ_S_ARB, 0x01020101);
1550 WREG32(mmTPC5_RTR_HBW_WR_RQ_E_ARB, 0x02020602);
1551 WREG32(mmTPC5_RTR_HBW_RD_RS_N_ARB, 0x01070201);
1552 WREG32(mmTPC5_RTR_HBW_RD_RS_S_ARB, 0x01020201);
1553 WREG32(mmTPC5_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1554 WREG32(mmTPC5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1555 WREG32(mmTPC5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1556 WREG32(mmTPC5_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1558 WREG32(mmTPC6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1559 WREG32(mmTPC6_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1560 WREG32(mmTPC6_RTR_HBW_RD_RQ_E_ARB, 0x01010601);
1561 WREG32(mmTPC6_RTR_HBW_WR_RQ_N_ARB, 0x01010101);
1562 WREG32(mmTPC6_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1563 WREG32(mmTPC6_RTR_HBW_WR_RQ_E_ARB, 0x02020702);
1564 WREG32(mmTPC6_RTR_HBW_RD_RS_N_ARB, 0x01010101);
1565 WREG32(mmTPC6_RTR_HBW_RD_RS_S_ARB, 0x01010101);
1566 WREG32(mmTPC6_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1567 WREG32(mmTPC6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1568 WREG32(mmTPC6_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1569 WREG32(mmTPC6_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1572 WREG32(mmMME1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1573 WREG32(mmMME2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1574 WREG32(mmMME3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1575 WREG32(mmMME4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1576 WREG32(mmMME5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1577 WREG32(mmMME6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1579 WREG32(mmTPC0_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1580 WREG32(mmTPC1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1581 WREG32(mmTPC2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1582 WREG32(mmTPC3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1583 WREG32(mmTPC4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1584 WREG32(mmTPC5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1585 WREG32(mmTPC6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1586 WREG32(mmTPC7_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1588 WREG32(mmPCI_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1589 WREG32(mmDMA_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1593 WREG32(mmMME1_RTR_SCRAMB_EN + offset,
1595 WREG32(mmMME1_RTR_NON_LIN_SCRAMB + offset,
1604 WREG32(mmTPC0_CFG_TPC_INTR_MASK + offset, tpc_intr_mask);
1606 WREG32(mmTPC0_NRTR_SCRAMB_EN + offset,
1608 WREG32(mmTPC0_NRTR_NON_LIN_SCRAMB + offset,
1615 WREG32(mmDMA_NRTR_SCRAMB_EN, 1 << DMA_NRTR_SCRAMB_EN_VAL_SHIFT);
1616 WREG32(mmDMA_NRTR_NON_LIN_SCRAMB,
1619 WREG32(mmPCI_NRTR_SCRAMB_EN, 1 << PCI_NRTR_SCRAMB_EN_VAL_SHIFT);
1620 WREG32(mmPCI_NRTR_NON_LIN_SCRAMB,
1630 WREG32(mmDMA_CH_1_CFG0, 0x0fff00F0);
1632 WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
1657 WREG32(mmMME_QM_PQ_BASE_LO, lower_32_bits(qman_base_addr));
1658 WREG32(mmMME_QM_PQ_BASE_HI, upper_32_bits(qman_base_addr));
1659 WREG32(mmMME_QM_PQ_SIZE, ilog2(MME_QMAN_LENGTH));
1660 WREG32(mmMME_QM_PQ_PI, 0);
1661 WREG32(mmMME_QM_PQ_CI, 0);
1662 WREG32(mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET, 0x10C0);
1663 WREG32(mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET, 0x10C4);
1664 WREG32(mmMME_QM_CP_LDMA_TSIZE_OFFSET, 0x10C8);
1665 WREG32(mmMME_QM_CP_LDMA_COMMIT_OFFSET, 0x10CC);
1667 WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1668 WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1669 WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1670 WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1673 WREG32(mmMME_QM_CQ_CFG1, 0x00080008);
1675 WREG32(mmMME_QM_GLBL_ERR_ADDR_LO, gic_base_lo);
1676 WREG32(mmMME_QM_GLBL_ERR_ADDR_HI, gic_base_hi);
1678 WREG32(mmMME_QM_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_QM);
1680 WREG32(mmMME_QM_GLBL_ERR_CFG, QMAN_MME_ERR_MSG_EN);
1682 WREG32(mmMME_QM_GLBL_PROT, QMAN_MME_ERR_PROT);
1684 WREG32(mmMME_QM_GLBL_CFG0, QMAN_MME_ENABLE);
1703 WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1704 WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1705 WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1706 WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1709 WREG32(mmMME_CMDQ_CQ_CFG1, 0x00140014);
1711 WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_LO, gic_base_lo);
1712 WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_HI, gic_base_hi);
1714 WREG32(mmMME_CMDQ_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_CMDQ);
1716 WREG32(mmMME_CMDQ_GLBL_ERR_CFG, CMDQ_MME_ERR_MSG_EN);
1718 WREG32(mmMME_CMDQ_GLBL_PROT, CMDQ_MME_ERR_PROT);
1720 WREG32(mmMME_CMDQ_GLBL_CFG0, CMDQ_MME_ENABLE);
1734 WREG32(mmMME_SM_BASE_ADDRESS_LOW, so_base_lo);
1735 WREG32(mmMME_SM_BASE_ADDRESS_HIGH, so_base_hi);
1763 WREG32(mmTPC0_QM_PQ_BASE_LO + reg_off, lower_32_bits(qman_base_addr));
1764 WREG32(mmTPC0_QM_PQ_BASE_HI + reg_off, upper_32_bits(qman_base_addr));
1765 WREG32(mmTPC0_QM_PQ_SIZE + reg_off, ilog2(TPC_QMAN_LENGTH));
1766 WREG32(mmTPC0_QM_PQ_PI + reg_off, 0);
1767 WREG32(mmTPC0_QM_PQ_CI + reg_off, 0);
1768 WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET + reg_off, 0x10C0);
1769 WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET + reg_off, 0x10C4);
1770 WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET + reg_off, 0x10C8);
1771 WREG32(mmTPC0_QM_CP_LDMA_COMMIT_OFFSET + reg_off, 0x10CC);
1773 WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1774 WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1775 WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1776 WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1778 WREG32(mmTPC0_QM_CQ_CFG1 + reg_off, 0x00080008);
1780 WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1781 WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1783 WREG32(mmTPC0_QM_GLBL_ERR_WDATA + reg_off,
1786 WREG32(mmTPC0_QM_GLBL_ERR_CFG + reg_off, QMAN_TPC_ERR_MSG_EN);
1788 WREG32(mmTPC0_QM_GLBL_PROT + reg_off, QMAN_TPC_ERR_PROT);
1790 WREG32(mmTPC0_QM_GLBL_CFG0 + reg_off, QMAN_TPC_ENABLE);
1810 WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1811 WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1812 WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1813 WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1815 WREG32(mmTPC0_CMDQ_CQ_CFG1 + reg_off, 0x00140014);
1817 WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1818 WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1820 WREG32(mmTPC0_CMDQ_GLBL_ERR_WDATA + reg_off,
1823 WREG32(mmTPC0_CMDQ_GLBL_ERR_CFG + reg_off, CMDQ_TPC_ERR_MSG_EN);
1825 WREG32(mmTPC0_CMDQ_GLBL_PROT + reg_off, CMDQ_TPC_ERR_PROT);
1827 WREG32(mmTPC0_CMDQ_GLBL_CFG0 + reg_off, CMDQ_TPC_ENABLE);
1845 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_LOW + i * cfg_off,
1847 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_HIGH + i * cfg_off,
1879 WREG32(mmMME_QM_GLBL_CFG0, 0);
1880 WREG32(mmMME_CMDQ_GLBL_CFG0, 0);
1886 WREG32(mmTPC0_QM_GLBL_CFG0, 0);
1887 WREG32(mmTPC0_CMDQ_GLBL_CFG0, 0);
1889 WREG32(mmTPC1_QM_GLBL_CFG0, 0);
1890 WREG32(mmTPC1_CMDQ_GLBL_CFG0, 0);
1892 WREG32(mmTPC2_QM_GLBL_CFG0, 0);
1893 WREG32(mmTPC2_CMDQ_GLBL_CFG0, 0);
1895 WREG32(mmTPC3_QM_GLBL_CFG0, 0);
1896 WREG32(mmTPC3_CMDQ_GLBL_CFG0, 0);
1898 WREG32(mmTPC4_QM_GLBL_CFG0, 0);
1899 WREG32(mmTPC4_CMDQ_GLBL_CFG0, 0);
1901 WREG32(mmTPC5_QM_GLBL_CFG0, 0);
1902 WREG32(mmTPC5_CMDQ_GLBL_CFG0, 0);
1904 WREG32(mmTPC6_QM_GLBL_CFG0, 0);
1905 WREG32(mmTPC6_CMDQ_GLBL_CFG0, 0);
1907 WREG32(mmTPC7_QM_GLBL_CFG0, 0);
1908 WREG32(mmTPC7_CMDQ_GLBL_CFG0, 0);
2127 WREG32(mmDMA_QM_0_GLBL_CFG1, 1 << DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT);
2128 WREG32(mmDMA_QM_1_GLBL_CFG1, 1 << DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT);
2129 WREG32(mmDMA_QM_2_GLBL_CFG1, 1 << DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT);
2130 WREG32(mmDMA_QM_3_GLBL_CFG1, 1 << DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT);
2131 WREG32(mmDMA_QM_4_GLBL_CFG1, 1 << DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT);
2141 WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
2142 WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC1_CFG_TPC_STALL_V_SHIFT);
2143 WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC2_CFG_TPC_STALL_V_SHIFT);
2144 WREG32(mmTPC3_CFG_TPC_STALL, 1 << TPC3_CFG_TPC_STALL_V_SHIFT);
2145 WREG32(mmTPC4_CFG_TPC_STALL, 1 << TPC4_CFG_TPC_STALL_V_SHIFT);
2146 WREG32(mmTPC5_CFG_TPC_STALL, 1 << TPC5_CFG_TPC_STALL_V_SHIFT);
2147 WREG32(mmTPC6_CFG_TPC_STALL, 1 << TPC6_CFG_TPC_STALL_V_SHIFT);
2148 WREG32(mmTPC7_CFG_TPC_STALL, 1 << TPC7_CFG_TPC_STALL_V_SHIFT);
2158 WREG32(mmMME_STALL, 0xFFFFFFFF);
2252 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
2255 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0xC, 0);
2256 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0x8, 0);
2259 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 1);
2265 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
2423 WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT);
2424 WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT);
2425 WREG32(MMU_ASID_BUSY, 0x80000000 | asid);
2475 WREG32(mmSTLB_CACHE_INV_BASE_39_8,
2477 WREG32(mmSTLB_CACHE_INV_BASE_49_40, MMU_CACHE_MNG_ADDR >> 40);
2486 WREG32(mmMMU_MMU_ENABLE, 1);
2487 WREG32(mmMMU_SPI_MASK, 0xF);
2519 WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY);
2597 WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_GOTO_WFE);
2598 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2607 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, RESET_ALL);
2612 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, DMA_MME_TPC_RESET);
2634 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2640 WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START,
2643 WREG32(mmPSOC_GLOBAL_CONF_SW_BTM_FSM,
2761 WREG32(db_reg_offset, db_value);
2764 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
3433 dev_dbg(hdev->dev, "WREG32 packet details:\n");
3439 dev_err(hdev->dev, "WREG32 packet with illegal address 0x%x\n",
3458 dev_err(hdev->dev, "WREG32 packet with illegal value 0x%x\n",
4003 WREG32(mmCPU_EQ_CI, val);
4022 WREG32(mmSYNC_MNGR_SOB_OBJ_0 + i, 0);
4025 WREG32(mmSYNC_MNGR_MON_STATUS_0 + i, 0);
4109 WREG32(addr - CFG_BASE, val);
4195 WREG32(addr - CFG_BASE, lower_32_bits(val));
4196 WREG32(addr + sizeof(u32) - CFG_BASE, upper_32_bits(val));
4450 WREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD, 0);
4455 WREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD, 0);
4460 WREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD, 0);
4465 WREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD, 0);
4487 WREG32(mmMMU_PAGE_ERROR_CAPTURE, 0);
4827 WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO, lower_32_bits(sob_addr));
4832 WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO + channel_off * dma_id,
4836 WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
4920 WREG32(mmCPU_IF_ARUSER_OVR_EN, 0x7FF);
4921 WREG32(mmCPU_IF_AWUSER_OVR_EN, 0x7FF);
4962 WREG32(mmCPU_IF_ARUSER_OVR_EN, 0);
4963 WREG32(mmCPU_IF_AWUSER_OVR_EN, 0);
5033 WREG32(mmSTLB_INV_ALL_START, 1);
5087 WREG32(mmSTLB_CACHE_INV,