1 // SPDX-License-Identifier: GPL-2.0
2
3 /*
4 * Copyright 2016-2018 HabanaLabs, Ltd.
5 * All Rights Reserved.
6 */
7
8 #include "gaudiP.h"
9 #include "../include/gaudi/gaudi_coresight.h"
10 #include "../include/gaudi/asic_reg/gaudi_regs.h"
11 #include "../include/gaudi/gaudi_masks.h"
12 #include "../include/gaudi/gaudi_reg_map.h"
13
14 #include <uapi/misc/habanalabs.h>
15 #include <linux/coresight.h>
16
17 #define SPMU_SECTION_SIZE MME0_ACC_SPMU_MAX_OFFSET
18 #define SPMU_EVENT_TYPES_OFFSET 0x400
19 #define SPMU_MAX_COUNTERS 6
20
21 static u64 debug_stm_regs[GAUDI_STM_LAST + 1] = {
22 [GAUDI_STM_MME0_ACC] = mmMME0_ACC_STM_BASE,
23 [GAUDI_STM_MME0_SBAB] = mmMME0_SBAB_STM_BASE,
24 [GAUDI_STM_MME0_CTRL] = mmMME0_CTRL_STM_BASE,
25 [GAUDI_STM_MME1_ACC] = mmMME1_ACC_STM_BASE,
26 [GAUDI_STM_MME1_SBAB] = mmMME1_SBAB_STM_BASE,
27 [GAUDI_STM_MME1_CTRL] = mmMME1_CTRL_STM_BASE,
28 [GAUDI_STM_MME2_ACC] = mmMME2_ACC_STM_BASE,
29 [GAUDI_STM_MME2_SBAB] = mmMME2_SBAB_STM_BASE,
30 [GAUDI_STM_MME2_CTRL] = mmMME2_CTRL_STM_BASE,
31 [GAUDI_STM_MME3_ACC] = mmMME3_ACC_STM_BASE,
32 [GAUDI_STM_MME3_SBAB] = mmMME3_SBAB_STM_BASE,
33 [GAUDI_STM_MME3_CTRL] = mmMME3_CTRL_STM_BASE,
34 [GAUDI_STM_DMA_IF_W_S] = mmDMA_IF_W_S_STM_BASE,
35 [GAUDI_STM_DMA_IF_E_S] = mmDMA_IF_E_S_STM_BASE,
36 [GAUDI_STM_DMA_IF_W_N] = mmDMA_IF_W_N_STM_BASE,
37 [GAUDI_STM_DMA_IF_E_N] = mmDMA_IF_E_N_STM_BASE,
38 [GAUDI_STM_CPU] = mmCPU_STM_BASE,
39 [GAUDI_STM_DMA_CH_0_CS] = mmDMA_CH_0_CS_STM_BASE,
40 [GAUDI_STM_DMA_CH_1_CS] = mmDMA_CH_1_CS_STM_BASE,
41 [GAUDI_STM_DMA_CH_2_CS] = mmDMA_CH_2_CS_STM_BASE,
42 [GAUDI_STM_DMA_CH_3_CS] = mmDMA_CH_3_CS_STM_BASE,
43 [GAUDI_STM_DMA_CH_4_CS] = mmDMA_CH_4_CS_STM_BASE,
44 [GAUDI_STM_DMA_CH_5_CS] = mmDMA_CH_5_CS_STM_BASE,
45 [GAUDI_STM_DMA_CH_6_CS] = mmDMA_CH_6_CS_STM_BASE,
46 [GAUDI_STM_DMA_CH_7_CS] = mmDMA_CH_7_CS_STM_BASE,
47 [GAUDI_STM_PCIE] = mmPCIE_STM_BASE,
48 [GAUDI_STM_MMU_CS] = mmMMU_CS_STM_BASE,
49 [GAUDI_STM_PSOC] = mmPSOC_STM_BASE,
50 [GAUDI_STM_NIC0_0] = mmSTM_0_NIC0_DBG_BASE,
51 [GAUDI_STM_NIC0_1] = mmSTM_1_NIC0_DBG_BASE,
52 [GAUDI_STM_NIC1_0] = mmSTM_0_NIC1_DBG_BASE,
53 [GAUDI_STM_NIC1_1] = mmSTM_1_NIC1_DBG_BASE,
54 [GAUDI_STM_NIC2_0] = mmSTM_0_NIC2_DBG_BASE,
55 [GAUDI_STM_NIC2_1] = mmSTM_1_NIC2_DBG_BASE,
56 [GAUDI_STM_NIC3_0] = mmSTM_0_NIC3_DBG_BASE,
57 [GAUDI_STM_NIC3_1] = mmSTM_1_NIC3_DBG_BASE,
58 [GAUDI_STM_NIC4_0] = mmSTM_0_NIC4_DBG_BASE,
59 [GAUDI_STM_NIC4_1] = mmSTM_1_NIC4_DBG_BASE,
60 [GAUDI_STM_TPC0_EML] = mmTPC0_EML_STM_BASE,
61 [GAUDI_STM_TPC1_EML] = mmTPC1_EML_STM_BASE,
62 [GAUDI_STM_TPC2_EML] = mmTPC2_EML_STM_BASE,
63 [GAUDI_STM_TPC3_EML] = mmTPC3_EML_STM_BASE,
64 [GAUDI_STM_TPC4_EML] = mmTPC4_EML_STM_BASE,
65 [GAUDI_STM_TPC5_EML] = mmTPC5_EML_STM_BASE,
66 [GAUDI_STM_TPC6_EML] = mmTPC6_EML_STM_BASE,
67 [GAUDI_STM_TPC7_EML] = mmTPC7_EML_STM_BASE
68 };
69
70 static u64 debug_etf_regs[GAUDI_ETF_LAST + 1] = {
71 [GAUDI_ETF_MME0_ACC] = mmMME0_ACC_ETF_BASE,
72 [GAUDI_ETF_MME0_SBAB] = mmMME0_SBAB_ETF_BASE,
73 [GAUDI_ETF_MME0_CTRL] = mmMME0_CTRL_ETF_BASE,
74 [GAUDI_ETF_MME1_ACC] = mmMME1_ACC_ETF_BASE,
75 [GAUDI_ETF_MME1_SBAB] = mmMME1_SBAB_ETF_BASE,
76 [GAUDI_ETF_MME1_CTRL] = mmMME1_CTRL_ETF_BASE,
77 [GAUDI_ETF_MME2_ACC] = mmMME2_MME2_ACC_ETF_BASE,
78 [GAUDI_ETF_MME2_SBAB] = mmMME2_SBAB_ETF_BASE,
79 [GAUDI_ETF_MME2_CTRL] = mmMME2_CTRL_ETF_BASE,
80 [GAUDI_ETF_MME3_ACC] = mmMME3_ACC_ETF_BASE,
81 [GAUDI_ETF_MME3_SBAB] = mmMME3_SBAB_ETF_BASE,
82 [GAUDI_ETF_MME3_CTRL] = mmMME3_CTRL_ETF_BASE,
83 [GAUDI_ETF_DMA_IF_W_S] = mmDMA_IF_W_S_ETF_BASE,
84 [GAUDI_ETF_DMA_IF_E_S] = mmDMA_IF_E_S_ETF_BASE,
85 [GAUDI_ETF_DMA_IF_W_N] = mmDMA_IF_W_N_ETF_BASE,
86 [GAUDI_ETF_DMA_IF_E_N] = mmDMA_IF_E_N_ETF_BASE,
87 [GAUDI_ETF_CPU_0] = mmCPU_ETF_0_BASE,
88 [GAUDI_ETF_CPU_1] = mmCPU_ETF_1_BASE,
89 [GAUDI_ETF_CPU_TRACE] = mmCPU_ETF_TRACE_BASE,
90 [GAUDI_ETF_DMA_CH_0_CS] = mmDMA_CH_0_CS_ETF_BASE,
91 [GAUDI_ETF_DMA_CH_1_CS] = mmDMA_CH_1_CS_ETF_BASE,
92 [GAUDI_ETF_DMA_CH_2_CS] = mmDMA_CH_2_CS_ETF_BASE,
93 [GAUDI_ETF_DMA_CH_3_CS] = mmDMA_CH_3_CS_ETF_BASE,
94 [GAUDI_ETF_DMA_CH_4_CS] = mmDMA_CH_4_CS_ETF_BASE,
95 [GAUDI_ETF_DMA_CH_5_CS] = mmDMA_CH_5_CS_ETF_BASE,
96 [GAUDI_ETF_DMA_CH_6_CS] = mmDMA_CH_6_CS_ETF_BASE,
97 [GAUDI_ETF_DMA_CH_7_CS] = mmDMA_CH_7_CS_ETF_BASE,
98 [GAUDI_ETF_PCIE] = mmPCIE_ETF_BASE,
99 [GAUDI_ETF_MMU_CS] = mmMMU_CS_ETF_BASE,
100 [GAUDI_ETF_PSOC] = mmPSOC_ETF_BASE,
101 [GAUDI_ETF_NIC0_0] = mmETF_0_NIC0_DBG_BASE,
102 [GAUDI_ETF_NIC0_1] = mmETF_1_NIC0_DBG_BASE,
103 [GAUDI_ETF_NIC1_0] = mmETF_0_NIC1_DBG_BASE,
104 [GAUDI_ETF_NIC1_1] = mmETF_1_NIC1_DBG_BASE,
105 [GAUDI_ETF_NIC2_0] = mmETF_0_NIC2_DBG_BASE,
106 [GAUDI_ETF_NIC2_1] = mmETF_1_NIC2_DBG_BASE,
107 [GAUDI_ETF_NIC3_0] = mmETF_0_NIC3_DBG_BASE,
108 [GAUDI_ETF_NIC3_1] = mmETF_1_NIC3_DBG_BASE,
109 [GAUDI_ETF_NIC4_0] = mmETF_0_NIC4_DBG_BASE,
110 [GAUDI_ETF_NIC4_1] = mmETF_1_NIC4_DBG_BASE,
111 [GAUDI_ETF_TPC0_EML] = mmTPC0_EML_ETF_BASE,
112 [GAUDI_ETF_TPC1_EML] = mmTPC1_EML_ETF_BASE,
113 [GAUDI_ETF_TPC2_EML] = mmTPC2_EML_ETF_BASE,
114 [GAUDI_ETF_TPC3_EML] = mmTPC3_EML_ETF_BASE,
115 [GAUDI_ETF_TPC4_EML] = mmTPC4_EML_ETF_BASE,
116 [GAUDI_ETF_TPC5_EML] = mmTPC5_EML_ETF_BASE,
117 [GAUDI_ETF_TPC6_EML] = mmTPC6_EML_ETF_BASE,
118 [GAUDI_ETF_TPC7_EML] = mmTPC7_EML_ETF_BASE
119 };
120
121 static u64 debug_funnel_regs[GAUDI_FUNNEL_LAST + 1] = {
122 [GAUDI_FUNNEL_MME0_ACC] = mmMME0_ACC_FUNNEL_BASE,
123 [GAUDI_FUNNEL_MME1_ACC] = mmMME1_ACC_FUNNEL_BASE,
124 [GAUDI_FUNNEL_MME2_ACC] = mmMME2_ACC_FUNNEL_BASE,
125 [GAUDI_FUNNEL_MME3_ACC] = mmMME3_ACC_FUNNEL_BASE,
126 [GAUDI_FUNNEL_SRAM_Y0_X0] = mmSRAM_Y0_X0_FUNNEL_BASE,
127 [GAUDI_FUNNEL_SRAM_Y0_X1] = mmSRAM_Y0_X1_FUNNEL_BASE,
128 [GAUDI_FUNNEL_SRAM_Y0_X2] = mmSRAM_Y0_X2_FUNNEL_BASE,
129 [GAUDI_FUNNEL_SRAM_Y0_X3] = mmSRAM_Y0_X3_FUNNEL_BASE,
130 [GAUDI_FUNNEL_SRAM_Y0_X4] = mmSRAM_Y0_X4_FUNNEL_BASE,
131 [GAUDI_FUNNEL_SRAM_Y0_X5] = mmSRAM_Y0_X5_FUNNEL_BASE,
132 [GAUDI_FUNNEL_SRAM_Y0_X6] = mmSRAM_Y0_X6_FUNNEL_BASE,
133 [GAUDI_FUNNEL_SRAM_Y0_X7] = mmSRAM_Y0_X7_FUNNEL_BASE,
134 [GAUDI_FUNNEL_SRAM_Y1_X0] = mmSRAM_Y1_X0_FUNNEL_BASE,
135 [GAUDI_FUNNEL_SRAM_Y1_X1] = mmSRAM_Y1_X1_FUNNEL_BASE,
136 [GAUDI_FUNNEL_SRAM_Y1_X2] = mmSRAM_Y1_X2_FUNNEL_BASE,
137 [GAUDI_FUNNEL_SRAM_Y1_X3] = mmSRAM_Y1_X3_FUNNEL_BASE,
138 [GAUDI_FUNNEL_SRAM_Y1_X4] = mmSRAM_Y1_X4_FUNNEL_BASE,
139 [GAUDI_FUNNEL_SRAM_Y1_X5] = mmSRAM_Y1_X5_FUNNEL_BASE,
140 [GAUDI_FUNNEL_SRAM_Y1_X6] = mmSRAM_Y1_X6_FUNNEL_BASE,
141 [GAUDI_FUNNEL_SRAM_Y1_X7] = mmSRAM_Y1_X7_FUNNEL_BASE,
142 [GAUDI_FUNNEL_SRAM_Y2_X0] = mmSRAM_Y2_X0_FUNNEL_BASE,
143 [GAUDI_FUNNEL_SRAM_Y2_X1] = mmSRAM_Y2_X1_FUNNEL_BASE,
144 [GAUDI_FUNNEL_SRAM_Y2_X2] = mmSRAM_Y2_X2_FUNNEL_BASE,
145 [GAUDI_FUNNEL_SRAM_Y2_X3] = mmSRAM_Y2_X3_FUNNEL_BASE,
146 [GAUDI_FUNNEL_SRAM_Y2_X4] = mmSRAM_Y2_X4_FUNNEL_BASE,
147 [GAUDI_FUNNEL_SRAM_Y2_X5] = mmSRAM_Y2_X5_FUNNEL_BASE,
148 [GAUDI_FUNNEL_SRAM_Y2_X6] = mmSRAM_Y2_X6_FUNNEL_BASE,
149 [GAUDI_FUNNEL_SRAM_Y2_X7] = mmSRAM_Y2_X7_FUNNEL_BASE,
150 [GAUDI_FUNNEL_SRAM_Y3_X0] = mmSRAM_Y3_X0_FUNNEL_BASE,
151 [GAUDI_FUNNEL_SRAM_Y3_X1] = mmSRAM_Y3_X1_FUNNEL_BASE,
152 [GAUDI_FUNNEL_SRAM_Y3_X2] = mmSRAM_Y3_X2_FUNNEL_BASE,
153 [GAUDI_FUNNEL_SRAM_Y3_X4] = mmSRAM_Y3_X4_FUNNEL_BASE,
154 [GAUDI_FUNNEL_SRAM_Y3_X3] = mmSRAM_Y3_X3_FUNNEL_BASE,
155 [GAUDI_FUNNEL_SRAM_Y3_X5] = mmSRAM_Y3_X5_FUNNEL_BASE,
156 [GAUDI_FUNNEL_SRAM_Y3_X6] = mmSRAM_Y3_X6_FUNNEL_BASE,
157 [GAUDI_FUNNEL_SRAM_Y3_X7] = mmSRAM_Y3_X7_FUNNEL_BASE,
158 [GAUDI_FUNNEL_SIF_0] = mmSIF_FUNNEL_0_BASE,
159 [GAUDI_FUNNEL_SIF_1] = mmSIF_FUNNEL_1_BASE,
160 [GAUDI_FUNNEL_SIF_2] = mmSIF_FUNNEL_2_BASE,
161 [GAUDI_FUNNEL_SIF_3] = mmSIF_FUNNEL_3_BASE,
162 [GAUDI_FUNNEL_SIF_4] = mmSIF_FUNNEL_4_BASE,
163 [GAUDI_FUNNEL_SIF_5] = mmSIF_FUNNEL_5_BASE,
164 [GAUDI_FUNNEL_SIF_6] = mmSIF_FUNNEL_6_BASE,
165 [GAUDI_FUNNEL_SIF_7] = mmSIF_FUNNEL_7_BASE,
166 [GAUDI_FUNNEL_NIF_0] = mmNIF_FUNNEL_0_BASE,
167 [GAUDI_FUNNEL_NIF_1] = mmNIF_FUNNEL_1_BASE,
168 [GAUDI_FUNNEL_NIF_2] = mmNIF_FUNNEL_2_BASE,
169 [GAUDI_FUNNEL_NIF_3] = mmNIF_FUNNEL_3_BASE,
170 [GAUDI_FUNNEL_NIF_4] = mmNIF_FUNNEL_4_BASE,
171 [GAUDI_FUNNEL_NIF_5] = mmNIF_FUNNEL_5_BASE,
172 [GAUDI_FUNNEL_NIF_6] = mmNIF_FUNNEL_6_BASE,
173 [GAUDI_FUNNEL_NIF_7] = mmNIF_FUNNEL_7_BASE,
174 [GAUDI_FUNNEL_DMA_IF_W_S] = mmDMA_IF_W_S_FUNNEL_BASE,
175 [GAUDI_FUNNEL_DMA_IF_E_S] = mmDMA_IF_E_S_FUNNEL_BASE,
176 [GAUDI_FUNNEL_DMA_IF_W_N] = mmDMA_IF_W_N_FUNNEL_BASE,
177 [GAUDI_FUNNEL_DMA_IF_E_N] = mmDMA_IF_E_N_FUNNEL_BASE,
178 [GAUDI_FUNNEL_CPU] = mmCPU_FUNNEL_BASE,
179 [GAUDI_FUNNEL_NIC_TPC_W_S] = mmNIC_TPC_FUNNEL_W_S_BASE,
180 [GAUDI_FUNNEL_NIC_TPC_E_S] = mmNIC_TPC_FUNNEL_E_S_BASE,
181 [GAUDI_FUNNEL_NIC_TPC_W_N] = mmNIC_TPC_FUNNEL_W_N_BASE,
182 [GAUDI_FUNNEL_NIC_TPC_E_N] = mmNIC_TPC_FUNNEL_E_N_BASE,
183 [GAUDI_FUNNEL_PCIE] = mmPCIE_FUNNEL_BASE,
184 [GAUDI_FUNNEL_PSOC] = mmPSOC_FUNNEL_BASE,
185 [GAUDI_FUNNEL_NIC0] = mmFUNNEL_NIC0_DBG_BASE,
186 [GAUDI_FUNNEL_NIC1] = mmFUNNEL_NIC1_DBG_BASE,
187 [GAUDI_FUNNEL_NIC2] = mmFUNNEL_NIC2_DBG_BASE,
188 [GAUDI_FUNNEL_NIC3] = mmFUNNEL_NIC3_DBG_BASE,
189 [GAUDI_FUNNEL_NIC4] = mmFUNNEL_NIC4_DBG_BASE,
190 [GAUDI_FUNNEL_TPC0_EML] = mmTPC0_EML_FUNNEL_BASE,
191 [GAUDI_FUNNEL_TPC1_EML] = mmTPC1_EML_FUNNEL_BASE,
192 [GAUDI_FUNNEL_TPC2_EML] = mmTPC2_EML_FUNNEL_BASE,
193 [GAUDI_FUNNEL_TPC3_EML] = mmTPC3_EML_FUNNEL_BASE,
194 [GAUDI_FUNNEL_TPC4_EML] = mmTPC4_EML_FUNNEL_BASE,
195 [GAUDI_FUNNEL_TPC5_EML] = mmTPC5_EML_FUNNEL_BASE,
196 [GAUDI_FUNNEL_TPC6_EML] = mmTPC6_EML_FUNNEL_BASE,
197 [GAUDI_FUNNEL_TPC7_EML] = mmTPC7_EML_FUNNEL_BASE
198 };
199
200 static u64 debug_bmon_regs[GAUDI_BMON_LAST + 1] = {
201 [GAUDI_BMON_MME0_ACC_0] = mmMME0_ACC_BMON0_BASE,
202 [GAUDI_BMON_MME0_SBAB_0] = mmMME0_SBAB_BMON0_BASE,
203 [GAUDI_BMON_MME0_SBAB_1] = mmMME0_SBAB_BMON1_BASE,
204 [GAUDI_BMON_MME0_CTRL_0] = mmMME0_CTRL_BMON0_BASE,
205 [GAUDI_BMON_MME0_CTRL_1] = mmMME0_CTRL_BMON1_BASE,
206 [GAUDI_BMON_MME1_ACC_0] = mmMME1_ACC_BMON0_BASE,
207 [GAUDI_BMON_MME1_SBAB_0] = mmMME1_SBAB_BMON0_BASE,
208 [GAUDI_BMON_MME1_SBAB_1] = mmMME1_SBAB_BMON1_BASE,
209 [GAUDI_BMON_MME1_CTRL_0] = mmMME1_CTRL_BMON0_BASE,
210 [GAUDI_BMON_MME1_CTRL_1] = mmMME1_CTRL_BMON1_BASE,
211 [GAUDI_BMON_MME2_ACC_0] = mmMME2_ACC_BMON0_BASE,
212 [GAUDI_BMON_MME2_SBAB_0] = mmMME2_SBAB_BMON0_BASE,
213 [GAUDI_BMON_MME2_SBAB_1] = mmMME2_SBAB_BMON1_BASE,
214 [GAUDI_BMON_MME2_CTRL_0] = mmMME2_CTRL_BMON0_BASE,
215 [GAUDI_BMON_MME2_CTRL_1] = mmMME2_CTRL_BMON1_BASE,
216 [GAUDI_BMON_MME3_ACC_0] = mmMME3_ACC_BMON0_BASE,
217 [GAUDI_BMON_MME3_SBAB_0] = mmMME3_SBAB_BMON0_BASE,
218 [GAUDI_BMON_MME3_SBAB_1] = mmMME3_SBAB_BMON1_BASE,
219 [GAUDI_BMON_MME3_CTRL_0] = mmMME3_CTRL_BMON0_BASE,
220 [GAUDI_BMON_MME3_CTRL_1] = mmMME3_CTRL_BMON1_BASE,
221 [GAUDI_BMON_DMA_IF_W_S_SOB_WR] = mmDMA_IF_W_S_SOB_WR_BMON_BASE,
222 [GAUDI_BMON_DMA_IF_W_S_0_WR] = mmDMA_IF_W_S_HBM0_WR_BMON_BASE,
223 [GAUDI_BMON_DMA_IF_W_S_0_RD] = mmDMA_IF_W_S_HBM0_RD_BMON_BASE,
224 [GAUDI_BMON_DMA_IF_W_S_1_WR] = mmDMA_IF_W_S_HBM1_WR_BMON_BASE,
225 [GAUDI_BMON_DMA_IF_W_S_1_RD] = mmDMA_IF_W_S_HBM1_RD_BMON_BASE,
226 [GAUDI_BMON_DMA_IF_E_S_SOB_WR] = mmDMA_IF_E_S_SOB_WR_BMON_BASE,
227 [GAUDI_BMON_DMA_IF_E_S_0_WR] = mmDMA_IF_E_S_HBM0_WR_BMON_BASE,
228 [GAUDI_BMON_DMA_IF_E_S_0_RD] = mmDMA_IF_E_S_HBM0_RD_BMON_BASE,
229 [GAUDI_BMON_DMA_IF_E_S_1_WR] = mmDMA_IF_E_S_HBM1_WR_BMON_BASE,
230 [GAUDI_BMON_DMA_IF_E_S_1_RD] = mmDMA_IF_E_S_HBM1_RD_BMON_BASE,
231 [GAUDI_BMON_DMA_IF_W_N_SOB_WR] = mmDMA_IF_W_N_SOB_WR_BMON_BASE,
232 [GAUDI_BMON_DMA_IF_W_N_HBM0_WR] = mmDMA_IF_W_N_HBM0_WR_BMON_BASE,
233 [GAUDI_BMON_DMA_IF_W_N_HBM0_RD] = mmDMA_IF_W_N_HBM0_RD_BMON_BASE,
234 [GAUDI_BMON_DMA_IF_W_N_HBM1_WR] = mmDMA_IF_W_N_HBM1_WR_BMON_BASE,
235 [GAUDI_BMON_DMA_IF_W_N_HBM1_RD] = mmDMA_IF_W_N_HBM1_RD_BMON_BASE,
236 [GAUDI_BMON_DMA_IF_E_N_SOB_WR] = mmDMA_IF_E_N_SOB_WR_BMON_BASE,
237 [GAUDI_BMON_DMA_IF_E_N_HBM0_WR] = mmDMA_IF_E_N_HBM0_WR_BMON_BASE,
238 [GAUDI_BMON_DMA_IF_E_N_HBM0_RD] = mmDMA_IF_E_N_HBM0_RD_BMON_BASE,
239 [GAUDI_BMON_DMA_IF_E_N_HBM1_WR] = mmDMA_IF_E_N_HBM1_WR_BMON_BASE,
240 [GAUDI_BMON_DMA_IF_E_N_HBM1_RD] = mmDMA_IF_E_N_HBM1_RD_BMON_BASE,
241 [GAUDI_BMON_CPU_WR] = mmCPU_WR_BMON_BASE,
242 [GAUDI_BMON_CPU_RD] = mmCPU_RD_BMON_BASE,
243 [GAUDI_BMON_DMA_CH_0_0] = mmDMA_CH_0_BMON_0_BASE,
244 [GAUDI_BMON_DMA_CH_0_1] = mmDMA_CH_0_BMON_1_BASE,
245 [GAUDI_BMON_DMA_CH_1_0] = mmDMA_CH_1_BMON_0_BASE,
246 [GAUDI_BMON_DMA_CH_1_1] = mmDMA_CH_1_BMON_1_BASE,
247 [GAUDI_BMON_DMA_CH_2_0] = mmDMA_CH_2_BMON_0_BASE,
248 [GAUDI_BMON_DMA_CH_2_1] = mmDMA_CH_2_BMON_1_BASE,
249 [GAUDI_BMON_DMA_CH_3_0] = mmDMA_CH_3_BMON_0_BASE,
250 [GAUDI_BMON_DMA_CH_3_1] = mmDMA_CH_3_BMON_1_BASE,
251 [GAUDI_BMON_DMA_CH_4_0] = mmDMA_CH_4_BMON_0_BASE,
252 [GAUDI_BMON_DMA_CH_4_1] = mmDMA_CH_4_BMON_1_BASE,
253 [GAUDI_BMON_DMA_CH_5_0] = mmDMA_CH_5_BMON_0_BASE,
254 [GAUDI_BMON_DMA_CH_5_1] = mmDMA_CH_5_BMON_1_BASE,
255 [GAUDI_BMON_DMA_CH_6_0] = mmDMA_CH_6_BMON_0_BASE,
256 [GAUDI_BMON_DMA_CH_6_1] = mmDMA_CH_6_BMON_1_BASE,
257 [GAUDI_BMON_DMA_CH_7_0] = mmDMA_CH_7_BMON_0_BASE,
258 [GAUDI_BMON_DMA_CH_7_1] = mmDMA_CH_7_BMON_1_BASE,
259 [GAUDI_BMON_PCIE_MSTR_WR] = mmPCIE_BMON_MSTR_WR_BASE,
260 [GAUDI_BMON_PCIE_MSTR_RD] = mmPCIE_BMON_MSTR_RD_BASE,
261 [GAUDI_BMON_PCIE_SLV_WR] = mmPCIE_BMON_SLV_WR_BASE,
262 [GAUDI_BMON_PCIE_SLV_RD] = mmPCIE_BMON_SLV_RD_BASE,
263 [GAUDI_BMON_MMU_0] = mmMMU_BMON_0_BASE,
264 [GAUDI_BMON_MMU_1] = mmMMU_BMON_1_BASE,
265 [GAUDI_BMON_NIC0_0] = mmBMON0_NIC0_DBG_BASE,
266 [GAUDI_BMON_NIC0_1] = mmBMON1_NIC0_DBG_BASE,
267 [GAUDI_BMON_NIC0_2] = mmBMON2_NIC0_DBG_BASE,
268 [GAUDI_BMON_NIC0_3] = mmBMON3_NIC0_DBG_BASE,
269 [GAUDI_BMON_NIC0_4] = mmBMON4_NIC0_DBG_BASE,
270 [GAUDI_BMON_NIC1_0] = mmBMON0_NIC1_DBG_BASE,
271 [GAUDI_BMON_NIC1_1] = mmBMON1_NIC1_DBG_BASE,
272 [GAUDI_BMON_NIC1_2] = mmBMON2_NIC1_DBG_BASE,
273 [GAUDI_BMON_NIC1_3] = mmBMON3_NIC1_DBG_BASE,
274 [GAUDI_BMON_NIC1_4] = mmBMON4_NIC1_DBG_BASE,
275 [GAUDI_BMON_NIC2_0] = mmBMON0_NIC2_DBG_BASE,
276 [GAUDI_BMON_NIC2_1] = mmBMON1_NIC2_DBG_BASE,
277 [GAUDI_BMON_NIC2_2] = mmBMON2_NIC2_DBG_BASE,
278 [GAUDI_BMON_NIC2_3] = mmBMON3_NIC2_DBG_BASE,
279 [GAUDI_BMON_NIC2_4] = mmBMON4_NIC2_DBG_BASE,
280 [GAUDI_BMON_NIC3_0] = mmBMON0_NIC3_DBG_BASE,
281 [GAUDI_BMON_NIC3_1] = mmBMON1_NIC3_DBG_BASE,
282 [GAUDI_BMON_NIC3_2] = mmBMON2_NIC3_DBG_BASE,
283 [GAUDI_BMON_NIC3_3] = mmBMON3_NIC3_DBG_BASE,
284 [GAUDI_BMON_NIC3_4] = mmBMON4_NIC3_DBG_BASE,
285 [GAUDI_BMON_NIC4_0] = mmBMON0_NIC4_DBG_BASE,
286 [GAUDI_BMON_NIC4_1] = mmBMON1_NIC4_DBG_BASE,
287 [GAUDI_BMON_NIC4_2] = mmBMON2_NIC4_DBG_BASE,
288 [GAUDI_BMON_NIC4_3] = mmBMON3_NIC4_DBG_BASE,
289 [GAUDI_BMON_NIC4_4] = mmBMON4_NIC4_DBG_BASE,
290 [GAUDI_BMON_TPC0_EML_0] = mmTPC0_EML_BUSMON_0_BASE,
291 [GAUDI_BMON_TPC0_EML_1] = mmTPC0_EML_BUSMON_1_BASE,
292 [GAUDI_BMON_TPC0_EML_2] = mmTPC0_EML_BUSMON_2_BASE,
293 [GAUDI_BMON_TPC0_EML_3] = mmTPC0_EML_BUSMON_3_BASE,
294 [GAUDI_BMON_TPC1_EML_0] = mmTPC1_EML_BUSMON_0_BASE,
295 [GAUDI_BMON_TPC1_EML_1] = mmTPC1_EML_BUSMON_1_BASE,
296 [GAUDI_BMON_TPC1_EML_2] = mmTPC1_EML_BUSMON_2_BASE,
297 [GAUDI_BMON_TPC1_EML_3] = mmTPC1_EML_BUSMON_3_BASE,
298 [GAUDI_BMON_TPC2_EML_0] = mmTPC2_EML_BUSMON_0_BASE,
299 [GAUDI_BMON_TPC2_EML_1] = mmTPC2_EML_BUSMON_1_BASE,
300 [GAUDI_BMON_TPC2_EML_2] = mmTPC2_EML_BUSMON_2_BASE,
301 [GAUDI_BMON_TPC2_EML_3] = mmTPC2_EML_BUSMON_3_BASE,
302 [GAUDI_BMON_TPC3_EML_0] = mmTPC3_EML_BUSMON_0_BASE,
303 [GAUDI_BMON_TPC3_EML_1] = mmTPC3_EML_BUSMON_1_BASE,
304 [GAUDI_BMON_TPC3_EML_2] = mmTPC3_EML_BUSMON_2_BASE,
305 [GAUDI_BMON_TPC3_EML_3] = mmTPC3_EML_BUSMON_3_BASE,
306 [GAUDI_BMON_TPC4_EML_0] = mmTPC4_EML_BUSMON_0_BASE,
307 [GAUDI_BMON_TPC4_EML_1] = mmTPC4_EML_BUSMON_1_BASE,
308 [GAUDI_BMON_TPC4_EML_2] = mmTPC4_EML_BUSMON_2_BASE,
309 [GAUDI_BMON_TPC4_EML_3] = mmTPC4_EML_BUSMON_3_BASE,
310 [GAUDI_BMON_TPC5_EML_0] = mmTPC5_EML_BUSMON_0_BASE,
311 [GAUDI_BMON_TPC5_EML_1] = mmTPC5_EML_BUSMON_1_BASE,
312 [GAUDI_BMON_TPC5_EML_2] = mmTPC5_EML_BUSMON_2_BASE,
313 [GAUDI_BMON_TPC5_EML_3] = mmTPC5_EML_BUSMON_3_BASE,
314 [GAUDI_BMON_TPC6_EML_0] = mmTPC6_EML_BUSMON_0_BASE,
315 [GAUDI_BMON_TPC6_EML_1] = mmTPC6_EML_BUSMON_1_BASE,
316 [GAUDI_BMON_TPC6_EML_2] = mmTPC6_EML_BUSMON_2_BASE,
317 [GAUDI_BMON_TPC6_EML_3] = mmTPC6_EML_BUSMON_3_BASE,
318 [GAUDI_BMON_TPC7_EML_0] = mmTPC7_EML_BUSMON_0_BASE,
319 [GAUDI_BMON_TPC7_EML_1] = mmTPC7_EML_BUSMON_1_BASE,
320 [GAUDI_BMON_TPC7_EML_2] = mmTPC7_EML_BUSMON_2_BASE,
321 [GAUDI_BMON_TPC7_EML_3] = mmTPC7_EML_BUSMON_3_BASE
322 };
323
324 static u64 debug_spmu_regs[GAUDI_SPMU_LAST + 1] = {
325 [GAUDI_SPMU_MME0_ACC] = mmMME0_ACC_SPMU_BASE,
326 [GAUDI_SPMU_MME0_SBAB] = mmMME0_SBAB_SPMU_BASE,
327 [GAUDI_SPMU_MME0_CTRL] = mmMME0_CTRL_SPMU_BASE,
328 [GAUDI_SPMU_MME1_ACC] = mmMME1_ACC_SPMU_BASE,
329 [GAUDI_SPMU_MME1_SBAB] = mmMME1_SBAB_SPMU_BASE,
330 [GAUDI_SPMU_MME1_CTRL] = mmMME1_CTRL_SPMU_BASE,
331 [GAUDI_SPMU_MME2_MME2_ACC] = mmMME2_ACC_SPMU_BASE,
332 [GAUDI_SPMU_MME2_SBAB] = mmMME2_SBAB_SPMU_BASE,
333 [GAUDI_SPMU_MME2_CTRL] = mmMME2_CTRL_SPMU_BASE,
334 [GAUDI_SPMU_MME3_ACC] = mmMME3_ACC_SPMU_BASE,
335 [GAUDI_SPMU_MME3_SBAB] = mmMME3_SBAB_SPMU_BASE,
336 [GAUDI_SPMU_MME3_CTRL] = mmMME3_CTRL_SPMU_BASE,
337 [GAUDI_SPMU_DMA_CH_0_CS] = mmDMA_CH_0_CS_SPMU_BASE,
338 [GAUDI_SPMU_DMA_CH_1_CS] = mmDMA_CH_1_CS_SPMU_BASE,
339 [GAUDI_SPMU_DMA_CH_2_CS] = mmDMA_CH_2_CS_SPMU_BASE,
340 [GAUDI_SPMU_DMA_CH_3_CS] = mmDMA_CH_3_CS_SPMU_BASE,
341 [GAUDI_SPMU_DMA_CH_4_CS] = mmDMA_CH_4_CS_SPMU_BASE,
342 [GAUDI_SPMU_DMA_CH_5_CS] = mmDMA_CH_5_CS_SPMU_BASE,
343 [GAUDI_SPMU_DMA_CH_6_CS] = mmDMA_CH_6_CS_SPMU_BASE,
344 [GAUDI_SPMU_DMA_CH_7_CS] = mmDMA_CH_7_CS_SPMU_BASE,
345 [GAUDI_SPMU_PCIE] = mmPCIE_SPMU_BASE,
346 [GAUDI_SPMU_MMU_CS] = mmMMU_CS_SPMU_BASE,
347 [GAUDI_SPMU_NIC0_0] = mmSPMU_0_NIC0_DBG_BASE,
348 [GAUDI_SPMU_NIC0_1] = mmSPMU_1_NIC0_DBG_BASE,
349 [GAUDI_SPMU_NIC1_0] = mmSPMU_0_NIC1_DBG_BASE,
350 [GAUDI_SPMU_NIC1_1] = mmSPMU_1_NIC1_DBG_BASE,
351 [GAUDI_SPMU_NIC2_0] = mmSPMU_0_NIC2_DBG_BASE,
352 [GAUDI_SPMU_NIC2_1] = mmSPMU_1_NIC2_DBG_BASE,
353 [GAUDI_SPMU_NIC3_0] = mmSPMU_0_NIC3_DBG_BASE,
354 [GAUDI_SPMU_NIC3_1] = mmSPMU_1_NIC3_DBG_BASE,
355 [GAUDI_SPMU_NIC4_0] = mmSPMU_0_NIC4_DBG_BASE,
356 [GAUDI_SPMU_NIC4_1] = mmSPMU_1_NIC4_DBG_BASE,
357 [GAUDI_SPMU_TPC0_EML] = mmTPC0_EML_SPMU_BASE,
358 [GAUDI_SPMU_TPC1_EML] = mmTPC1_EML_SPMU_BASE,
359 [GAUDI_SPMU_TPC2_EML] = mmTPC2_EML_SPMU_BASE,
360 [GAUDI_SPMU_TPC3_EML] = mmTPC3_EML_SPMU_BASE,
361 [GAUDI_SPMU_TPC4_EML] = mmTPC4_EML_SPMU_BASE,
362 [GAUDI_SPMU_TPC5_EML] = mmTPC5_EML_SPMU_BASE,
363 [GAUDI_SPMU_TPC6_EML] = mmTPC6_EML_SPMU_BASE,
364 [GAUDI_SPMU_TPC7_EML] = mmTPC7_EML_SPMU_BASE
365 };
366
gaudi_coresight_timeout(struct hl_device *hdev, u64 addr, int position, bool up)367 static int gaudi_coresight_timeout(struct hl_device *hdev, u64 addr,
368 int position, bool up)
369 {
370 int rc;
371 u32 val;
372
373 rc = hl_poll_timeout(
374 hdev,
375 addr,
376 val,
377 up ? val & BIT(position) : !(val & BIT(position)),
378 1000,
379 CORESIGHT_TIMEOUT_USEC);
380
381 if (rc) {
382 dev_err(hdev->dev,
383 "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n",
384 addr, position, up);
385 return -EFAULT;
386 }
387
388 return 0;
389 }
390
gaudi_config_stm(struct hl_device *hdev, struct hl_debug_params *params)391 static int gaudi_config_stm(struct hl_device *hdev,
392 struct hl_debug_params *params)
393 {
394 struct hl_debug_params_stm *input;
395 u64 base_reg;
396 u32 frequency;
397 int rc;
398
399 if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) {
400 dev_err(hdev->dev, "Invalid register index in STM\n");
401 return -EINVAL;
402 }
403
404 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE;
405
406 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
407
408 if (params->enable) {
409 input = params->input;
410
411 if (!input)
412 return -EINVAL;
413
414 WREG32(base_reg + 0xE80, 0x80004);
415 WREG32(base_reg + 0xD64, 7);
416 WREG32(base_reg + 0xD60, 0);
417 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask));
418 WREG32(base_reg + 0xD60, 1);
419 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask));
420 WREG32(base_reg + 0xE70, 0x10);
421 WREG32(base_reg + 0xE60, 0);
422 WREG32(base_reg + 0xE00, lower_32_bits(input->sp_mask));
423 WREG32(base_reg + 0xEF4, input->id);
424 WREG32(base_reg + 0xDF4, 0x80);
425 frequency = hdev->asic_prop.psoc_timestamp_frequency;
426 if (frequency == 0)
427 frequency = input->frequency;
428 WREG32(base_reg + 0xE8C, frequency);
429 WREG32(base_reg + 0xE90, 0x7FF);
430
431 /* SW-2176 - SW WA for HW bug */
432 if ((CFG_BASE + base_reg) >= mmDMA_CH_0_CS_STM_BASE &&
433 (CFG_BASE + base_reg) <= mmDMA_CH_7_CS_STM_BASE) {
434
435 WREG32(base_reg + 0xE68, 0xffff8005);
436 WREG32(base_reg + 0xE6C, 0x0);
437 }
438
439 WREG32(base_reg + 0xE80, 0x27 | (input->id << 16));
440 } else {
441 WREG32(base_reg + 0xE80, 4);
442 WREG32(base_reg + 0xD64, 0);
443 WREG32(base_reg + 0xD60, 1);
444 WREG32(base_reg + 0xD00, 0);
445 WREG32(base_reg + 0xD20, 0);
446 WREG32(base_reg + 0xD60, 0);
447 WREG32(base_reg + 0xE20, 0);
448 WREG32(base_reg + 0xE00, 0);
449 WREG32(base_reg + 0xDF4, 0x80);
450 WREG32(base_reg + 0xE70, 0);
451 WREG32(base_reg + 0xE60, 0);
452 WREG32(base_reg + 0xE64, 0);
453 WREG32(base_reg + 0xE8C, 0);
454
455 rc = gaudi_coresight_timeout(hdev, base_reg + 0xE80, 23, false);
456 if (rc) {
457 dev_err(hdev->dev,
458 "Failed to disable STM on timeout, error %d\n",
459 rc);
460 return rc;
461 }
462
463 WREG32(base_reg + 0xE80, 4);
464 }
465
466 return 0;
467 }
468
gaudi_config_etf(struct hl_device *hdev, struct hl_debug_params *params)469 static int gaudi_config_etf(struct hl_device *hdev,
470 struct hl_debug_params *params)
471 {
472 struct hl_debug_params_etf *input;
473 u64 base_reg;
474 u32 val;
475 int rc;
476
477 if (params->reg_idx >= ARRAY_SIZE(debug_etf_regs)) {
478 dev_err(hdev->dev, "Invalid register index in ETF\n");
479 return -EINVAL;
480 }
481
482 base_reg = debug_etf_regs[params->reg_idx] - CFG_BASE;
483
484 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
485
486 val = RREG32(base_reg + 0x304);
487 val |= 0x1000;
488 WREG32(base_reg + 0x304, val);
489 val |= 0x40;
490 WREG32(base_reg + 0x304, val);
491
492 rc = gaudi_coresight_timeout(hdev, base_reg + 0x304, 6, false);
493 if (rc) {
494 dev_err(hdev->dev,
495 "Failed to %s ETF on timeout, error %d\n",
496 params->enable ? "enable" : "disable", rc);
497 return rc;
498 }
499
500 rc = gaudi_coresight_timeout(hdev, base_reg + 0xC, 2, true);
501 if (rc) {
502 dev_err(hdev->dev,
503 "Failed to %s ETF on timeout, error %d\n",
504 params->enable ? "enable" : "disable", rc);
505 return rc;
506 }
507
508 WREG32(base_reg + 0x20, 0);
509
510 if (params->enable) {
511 input = params->input;
512
513 if (!input)
514 return -EINVAL;
515
516 WREG32(base_reg + 0x34, 0x3FFC);
517 WREG32(base_reg + 0x28, input->sink_mode);
518 WREG32(base_reg + 0x304, 0x4001);
519 WREG32(base_reg + 0x308, 0xA);
520 WREG32(base_reg + 0x20, 1);
521 } else {
522 WREG32(base_reg + 0x34, 0);
523 WREG32(base_reg + 0x28, 0);
524 WREG32(base_reg + 0x304, 0);
525 }
526
527 return 0;
528 }
529
gaudi_etr_validate_address(struct hl_device *hdev, u64 addr, u64 size, bool *is_host)530 static bool gaudi_etr_validate_address(struct hl_device *hdev, u64 addr,
531 u64 size, bool *is_host)
532 {
533 struct asic_fixed_properties *prop = &hdev->asic_prop;
534 struct gaudi_device *gaudi = hdev->asic_specific;
535
536 /* maximum address length is 50 bits */
537 if (addr >> 50) {
538 dev_err(hdev->dev,
539 "ETR buffer address shouldn't exceed 50 bits\n");
540 return false;
541 }
542
543 if (addr > (addr + size)) {
544 dev_err(hdev->dev,
545 "ETR buffer size %llu overflow\n", size);
546 return false;
547 }
548
549 /* PMMU and HPMMU addresses are equal, check only one of them */
550 if ((gaudi->hw_cap_initialized & HW_CAP_MMU) &&
551 hl_mem_area_inside_range(addr, size,
552 prop->pmmu.start_addr,
553 prop->pmmu.end_addr)) {
554 *is_host = true;
555 return true;
556 }
557
558 if (hl_mem_area_inside_range(addr, size,
559 prop->dram_user_base_address,
560 prop->dram_end_address))
561 return true;
562
563 if (hl_mem_area_inside_range(addr, size,
564 prop->sram_user_base_address,
565 prop->sram_end_address))
566 return true;
567
568 if (!(gaudi->hw_cap_initialized & HW_CAP_MMU))
569 dev_err(hdev->dev, "ETR buffer should be in SRAM/DRAM\n");
570
571 return false;
572 }
573
gaudi_config_etr(struct hl_device *hdev, struct hl_debug_params *params)574 static int gaudi_config_etr(struct hl_device *hdev,
575 struct hl_debug_params *params)
576 {
577 struct hl_debug_params_etr *input;
578 u64 msb;
579 u32 val;
580 int rc;
581
582 WREG32(mmPSOC_ETR_LAR, CORESIGHT_UNLOCK);
583
584 val = RREG32(mmPSOC_ETR_FFCR);
585 val |= 0x1000;
586 WREG32(mmPSOC_ETR_FFCR, val);
587 val |= 0x40;
588 WREG32(mmPSOC_ETR_FFCR, val);
589
590 rc = gaudi_coresight_timeout(hdev, mmPSOC_ETR_FFCR, 6, false);
591 if (rc) {
592 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",
593 params->enable ? "enable" : "disable", rc);
594 return rc;
595 }
596
597 rc = gaudi_coresight_timeout(hdev, mmPSOC_ETR_STS, 2, true);
598 if (rc) {
599 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",
600 params->enable ? "enable" : "disable", rc);
601 return rc;
602 }
603
604 WREG32(mmPSOC_ETR_CTL, 0);
605
606 if (params->enable) {
607 bool is_host = false;
608
609 input = params->input;
610
611 if (!input)
612 return -EINVAL;
613
614 if (input->buffer_size == 0) {
615 dev_err(hdev->dev,
616 "ETR buffer size should be bigger than 0\n");
617 return -EINVAL;
618 }
619
620 if (!gaudi_etr_validate_address(hdev,
621 input->buffer_address, input->buffer_size,
622 &is_host)) {
623 dev_err(hdev->dev, "ETR buffer address is invalid\n");
624 return -EINVAL;
625 }
626
627 gaudi_mmu_prepare_reg(hdev, mmPSOC_GLOBAL_CONF_TRACE_ARUSER,
628 hdev->compute_ctx->asid);
629 gaudi_mmu_prepare_reg(hdev, mmPSOC_GLOBAL_CONF_TRACE_AWUSER,
630 hdev->compute_ctx->asid);
631
632 msb = upper_32_bits(input->buffer_address) >> 8;
633 msb &= PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK;
634 WREG32(mmPSOC_GLOBAL_CONF_TRACE_ADDR, msb);
635
636 WREG32(mmPSOC_ETR_BUFWM, 0x3FFC);
637 WREG32(mmPSOC_ETR_RSZ, input->buffer_size);
638 WREG32(mmPSOC_ETR_MODE, input->sink_mode);
639 /* Workaround for H3 #HW-2075 bug: use small data chunks */
640 WREG32(mmPSOC_ETR_AXICTL, (is_host ? 0 : 0x700) |
641 PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT);
642 WREG32(mmPSOC_ETR_DBALO,
643 lower_32_bits(input->buffer_address));
644 WREG32(mmPSOC_ETR_DBAHI,
645 upper_32_bits(input->buffer_address));
646 WREG32(mmPSOC_ETR_FFCR, 3);
647 WREG32(mmPSOC_ETR_PSCR, 0xA);
648 WREG32(mmPSOC_ETR_CTL, 1);
649 } else {
650 WREG32(mmPSOC_ETR_BUFWM, 0);
651 WREG32(mmPSOC_ETR_RSZ, 0x400);
652 WREG32(mmPSOC_ETR_DBALO, 0);
653 WREG32(mmPSOC_ETR_DBAHI, 0);
654 WREG32(mmPSOC_ETR_PSCR, 0);
655 WREG32(mmPSOC_ETR_MODE, 0);
656 WREG32(mmPSOC_ETR_FFCR, 0);
657
658 if (params->output_size >= sizeof(u64)) {
659 u32 rwp, rwphi;
660
661 /*
662 * The trace buffer address is 50 bits wide. The end of
663 * the buffer is set in the RWP register (lower 32
664 * bits), and in the RWPHI register (upper 8 bits).
665 * The 10 msb of the 50-bit address are stored in a
666 * global configuration register.
667 */
668 rwp = RREG32(mmPSOC_ETR_RWP);
669 rwphi = RREG32(mmPSOC_ETR_RWPHI) & 0xff;
670 msb = RREG32(mmPSOC_GLOBAL_CONF_TRACE_ADDR) &
671 PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK;
672 *(u64 *) params->output = ((u64) msb << 40) |
673 ((u64) rwphi << 32) | rwp;
674 }
675 }
676
677 return 0;
678 }
679
gaudi_config_funnel(struct hl_device *hdev, struct hl_debug_params *params)680 static int gaudi_config_funnel(struct hl_device *hdev,
681 struct hl_debug_params *params)
682 {
683 u64 base_reg;
684
685 if (params->reg_idx >= ARRAY_SIZE(debug_funnel_regs)) {
686 dev_err(hdev->dev, "Invalid register index in FUNNEL\n");
687 return -EINVAL;
688 }
689
690 base_reg = debug_funnel_regs[params->reg_idx] - CFG_BASE;
691
692 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
693
694 WREG32(base_reg, params->enable ? 0x33F : 0);
695
696 return 0;
697 }
698
gaudi_config_bmon(struct hl_device *hdev, struct hl_debug_params *params)699 static int gaudi_config_bmon(struct hl_device *hdev,
700 struct hl_debug_params *params)
701 {
702 struct hl_debug_params_bmon *input;
703 u64 base_reg;
704
705 if (params->reg_idx >= ARRAY_SIZE(debug_bmon_regs)) {
706 dev_err(hdev->dev, "Invalid register index in BMON\n");
707 return -EINVAL;
708 }
709
710 base_reg = debug_bmon_regs[params->reg_idx] - CFG_BASE;
711
712 WREG32(base_reg + 0x104, 1);
713
714 if (params->enable) {
715 input = params->input;
716
717 if (!input)
718 return -EINVAL;
719
720 WREG32(base_reg + 0x200, lower_32_bits(input->start_addr0));
721 WREG32(base_reg + 0x204, upper_32_bits(input->start_addr0));
722 WREG32(base_reg + 0x208, lower_32_bits(input->addr_mask0));
723 WREG32(base_reg + 0x20C, upper_32_bits(input->addr_mask0));
724 WREG32(base_reg + 0x240, lower_32_bits(input->start_addr1));
725 WREG32(base_reg + 0x244, upper_32_bits(input->start_addr1));
726 WREG32(base_reg + 0x248, lower_32_bits(input->addr_mask1));
727 WREG32(base_reg + 0x24C, upper_32_bits(input->addr_mask1));
728 WREG32(base_reg + 0x224, 0);
729 WREG32(base_reg + 0x234, 0);
730 WREG32(base_reg + 0x30C, input->bw_win);
731 WREG32(base_reg + 0x308, input->win_capture);
732 WREG32(base_reg + 0x700, 0xA000B00 | (input->id << 12));
733 WREG32(base_reg + 0x708, 0xA000A00 | (input->id << 12));
734 WREG32(base_reg + 0x70C, 0xA000C00 | (input->id << 12));
735 WREG32(base_reg + 0x100, 0x11);
736 WREG32(base_reg + 0x304, 0x1);
737 } else {
738 WREG32(base_reg + 0x200, 0);
739 WREG32(base_reg + 0x204, 0);
740 WREG32(base_reg + 0x208, 0xFFFFFFFF);
741 WREG32(base_reg + 0x20C, 0xFFFFFFFF);
742 WREG32(base_reg + 0x240, 0);
743 WREG32(base_reg + 0x244, 0);
744 WREG32(base_reg + 0x248, 0xFFFFFFFF);
745 WREG32(base_reg + 0x24C, 0xFFFFFFFF);
746 WREG32(base_reg + 0x224, 0xFFFFFFFF);
747 WREG32(base_reg + 0x234, 0x1070F);
748 WREG32(base_reg + 0x30C, 0);
749 WREG32(base_reg + 0x308, 0xFFFF);
750 WREG32(base_reg + 0x700, 0xA000B00);
751 WREG32(base_reg + 0x708, 0xA000A00);
752 WREG32(base_reg + 0x70C, 0xA000C00);
753 WREG32(base_reg + 0x100, 1);
754 WREG32(base_reg + 0x304, 0);
755 WREG32(base_reg + 0x104, 0);
756 }
757
758 return 0;
759 }
760
gaudi_config_spmu(struct hl_device *hdev, struct hl_debug_params *params)761 static int gaudi_config_spmu(struct hl_device *hdev,
762 struct hl_debug_params *params)
763 {
764 u64 base_reg;
765 struct hl_debug_params_spmu *input = params->input;
766 u64 *output;
767 u32 output_arr_len;
768 u32 events_num;
769 u32 overflow_idx;
770 u32 cycle_cnt_idx;
771 int i;
772
773 if (params->reg_idx >= ARRAY_SIZE(debug_spmu_regs)) {
774 dev_err(hdev->dev, "Invalid register index in SPMU\n");
775 return -EINVAL;
776 }
777
778 base_reg = debug_spmu_regs[params->reg_idx] - CFG_BASE;
779
780 if (params->enable) {
781 input = params->input;
782
783 if (!input)
784 return -EINVAL;
785
786 if (input->event_types_num < 3) {
787 dev_err(hdev->dev,
788 "not enough event types values for SPMU enable\n");
789 return -EINVAL;
790 }
791
792 if (input->event_types_num > SPMU_MAX_COUNTERS) {
793 dev_err(hdev->dev,
794 "too many event types values for SPMU enable\n");
795 return -EINVAL;
796 }
797
798 WREG32(base_reg + 0xE04, 0x41013046);
799 WREG32(base_reg + 0xE04, 0x41013040);
800
801 for (i = 0 ; i < input->event_types_num ; i++)
802 WREG32(base_reg + SPMU_EVENT_TYPES_OFFSET + i * 4,
803 input->event_types[i]);
804
805 WREG32(base_reg + 0xE04, 0x41013041);
806 WREG32(base_reg + 0xC00, 0x8000003F);
807 } else {
808 output = params->output;
809 output_arr_len = params->output_size / 8;
810 events_num = output_arr_len - 2;
811 overflow_idx = output_arr_len - 2;
812 cycle_cnt_idx = output_arr_len - 1;
813
814 if (!output)
815 return -EINVAL;
816
817 if (output_arr_len < 3) {
818 dev_err(hdev->dev,
819 "not enough values for SPMU disable\n");
820 return -EINVAL;
821 }
822
823 if (events_num > SPMU_MAX_COUNTERS) {
824 dev_err(hdev->dev,
825 "too many events values for SPMU disable\n");
826 return -EINVAL;
827 }
828
829 WREG32(base_reg + 0xE04, 0x41013040);
830
831 for (i = 0 ; i < events_num ; i++)
832 output[i] = RREG32(base_reg + i * 8);
833
834 output[overflow_idx] = RREG32(base_reg + 0xCC0);
835
836 output[cycle_cnt_idx] = RREG32(base_reg + 0xFC);
837 output[cycle_cnt_idx] <<= 32;
838 output[cycle_cnt_idx] |= RREG32(base_reg + 0xF8);
839
840 WREG32(base_reg + 0xCC0, 0);
841 }
842
843 return 0;
844 }
845
gaudi_debug_coresight(struct hl_device *hdev, void *data)846 int gaudi_debug_coresight(struct hl_device *hdev, void *data)
847 {
848 struct hl_debug_params *params = data;
849 int rc = 0;
850
851 switch (params->op) {
852 case HL_DEBUG_OP_STM:
853 rc = gaudi_config_stm(hdev, params);
854 break;
855 case HL_DEBUG_OP_ETF:
856 rc = gaudi_config_etf(hdev, params);
857 break;
858 case HL_DEBUG_OP_ETR:
859 rc = gaudi_config_etr(hdev, params);
860 break;
861 case HL_DEBUG_OP_FUNNEL:
862 rc = gaudi_config_funnel(hdev, params);
863 break;
864 case HL_DEBUG_OP_BMON:
865 rc = gaudi_config_bmon(hdev, params);
866 break;
867 case HL_DEBUG_OP_SPMU:
868 rc = gaudi_config_spmu(hdev, params);
869 break;
870 case HL_DEBUG_OP_TIMESTAMP:
871 /* Do nothing as this opcode is deprecated */
872 break;
873
874 default:
875 dev_err(hdev->dev, "Unknown coresight id %d\n", params->op);
876 return -EINVAL;
877 }
878
879 /* Perform read from the device to flush all configuration */
880 RREG32(mmHW_STATE);
881
882 return rc;
883 }
884
gaudi_halt_coresight(struct hl_device *hdev)885 void gaudi_halt_coresight(struct hl_device *hdev)
886 {
887 struct hl_debug_params params = {};
888 int i, rc;
889
890 for (i = GAUDI_ETF_FIRST ; i <= GAUDI_ETF_LAST ; i++) {
891 params.reg_idx = i;
892 rc = gaudi_config_etf(hdev, ¶ms);
893 if (rc)
894 dev_err(hdev->dev, "halt ETF failed, %d/%d\n", rc, i);
895 }
896
897 rc = gaudi_config_etr(hdev, ¶ms);
898 if (rc)
899 dev_err(hdev->dev, "halt ETR failed, %d\n", rc);
900 }
901