Lines Matching refs:WREG32
812 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, GAUDI_EVENT_INTS_REGISTER);
1267 WREG32(mmNIF_RTR_CTRL_0_SCRAM_SRAM_EN,
1269 WREG32(mmNIF_RTR_CTRL_1_SCRAM_SRAM_EN,
1271 WREG32(mmNIF_RTR_CTRL_2_SCRAM_SRAM_EN,
1273 WREG32(mmNIF_RTR_CTRL_3_SCRAM_SRAM_EN,
1275 WREG32(mmNIF_RTR_CTRL_4_SCRAM_SRAM_EN,
1277 WREG32(mmNIF_RTR_CTRL_5_SCRAM_SRAM_EN,
1279 WREG32(mmNIF_RTR_CTRL_6_SCRAM_SRAM_EN,
1281 WREG32(mmNIF_RTR_CTRL_7_SCRAM_SRAM_EN,
1284 WREG32(mmSIF_RTR_CTRL_0_SCRAM_SRAM_EN,
1286 WREG32(mmSIF_RTR_CTRL_1_SCRAM_SRAM_EN,
1288 WREG32(mmSIF_RTR_CTRL_2_SCRAM_SRAM_EN,
1290 WREG32(mmSIF_RTR_CTRL_3_SCRAM_SRAM_EN,
1292 WREG32(mmSIF_RTR_CTRL_4_SCRAM_SRAM_EN,
1294 WREG32(mmSIF_RTR_CTRL_5_SCRAM_SRAM_EN,
1296 WREG32(mmSIF_RTR_CTRL_6_SCRAM_SRAM_EN,
1298 WREG32(mmSIF_RTR_CTRL_7_SCRAM_SRAM_EN,
1301 WREG32(mmDMA_IF_E_N_DOWN_CH0_SCRAM_SRAM_EN,
1303 WREG32(mmDMA_IF_E_N_DOWN_CH1_SCRAM_SRAM_EN,
1305 WREG32(mmDMA_IF_E_S_DOWN_CH0_SCRAM_SRAM_EN,
1307 WREG32(mmDMA_IF_E_S_DOWN_CH1_SCRAM_SRAM_EN,
1309 WREG32(mmDMA_IF_W_N_DOWN_CH0_SCRAM_SRAM_EN,
1311 WREG32(mmDMA_IF_W_N_DOWN_CH1_SCRAM_SRAM_EN,
1313 WREG32(mmDMA_IF_W_S_DOWN_CH0_SCRAM_SRAM_EN,
1315 WREG32(mmDMA_IF_W_S_DOWN_CH1_SCRAM_SRAM_EN,
1331 WREG32(mmNIF_RTR_CTRL_0_SCRAM_HBM_EN,
1333 WREG32(mmNIF_RTR_CTRL_1_SCRAM_HBM_EN,
1335 WREG32(mmNIF_RTR_CTRL_2_SCRAM_HBM_EN,
1337 WREG32(mmNIF_RTR_CTRL_3_SCRAM_HBM_EN,
1339 WREG32(mmNIF_RTR_CTRL_4_SCRAM_HBM_EN,
1341 WREG32(mmNIF_RTR_CTRL_5_SCRAM_HBM_EN,
1343 WREG32(mmNIF_RTR_CTRL_6_SCRAM_HBM_EN,
1345 WREG32(mmNIF_RTR_CTRL_7_SCRAM_HBM_EN,
1348 WREG32(mmSIF_RTR_CTRL_0_SCRAM_HBM_EN,
1350 WREG32(mmSIF_RTR_CTRL_1_SCRAM_HBM_EN,
1352 WREG32(mmSIF_RTR_CTRL_2_SCRAM_HBM_EN,
1354 WREG32(mmSIF_RTR_CTRL_3_SCRAM_HBM_EN,
1356 WREG32(mmSIF_RTR_CTRL_4_SCRAM_HBM_EN,
1358 WREG32(mmSIF_RTR_CTRL_5_SCRAM_HBM_EN,
1360 WREG32(mmSIF_RTR_CTRL_6_SCRAM_HBM_EN,
1362 WREG32(mmSIF_RTR_CTRL_7_SCRAM_HBM_EN,
1365 WREG32(mmDMA_IF_E_N_DOWN_CH0_SCRAM_HBM_EN,
1367 WREG32(mmDMA_IF_E_N_DOWN_CH1_SCRAM_HBM_EN,
1369 WREG32(mmDMA_IF_E_S_DOWN_CH0_SCRAM_HBM_EN,
1371 WREG32(mmDMA_IF_E_S_DOWN_CH1_SCRAM_HBM_EN,
1373 WREG32(mmDMA_IF_W_N_DOWN_CH0_SCRAM_HBM_EN,
1375 WREG32(mmDMA_IF_W_N_DOWN_CH1_SCRAM_HBM_EN,
1377 WREG32(mmDMA_IF_W_S_DOWN_CH0_SCRAM_HBM_EN,
1379 WREG32(mmDMA_IF_W_S_DOWN_CH1_SCRAM_HBM_EN,
1387 WREG32(mmSIF_RTR_CTRL_0_E2E_HBM_WR_SIZE, 247 >> 3);
1388 WREG32(mmSIF_RTR_CTRL_0_E2E_HBM_RD_SIZE, 785 >> 3);
1389 WREG32(mmSIF_RTR_CTRL_0_E2E_PCI_WR_SIZE, 49);
1390 WREG32(mmSIF_RTR_CTRL_0_E2E_PCI_RD_SIZE, 101);
1392 WREG32(mmSIF_RTR_CTRL_1_E2E_HBM_WR_SIZE, 275 >> 3);
1393 WREG32(mmSIF_RTR_CTRL_1_E2E_HBM_RD_SIZE, 614 >> 3);
1394 WREG32(mmSIF_RTR_CTRL_1_E2E_PCI_WR_SIZE, 1);
1395 WREG32(mmSIF_RTR_CTRL_1_E2E_PCI_RD_SIZE, 39);
1397 WREG32(mmSIF_RTR_CTRL_2_E2E_HBM_WR_SIZE, 1);
1398 WREG32(mmSIF_RTR_CTRL_2_E2E_HBM_RD_SIZE, 1);
1399 WREG32(mmSIF_RTR_CTRL_2_E2E_PCI_WR_SIZE, 1);
1400 WREG32(mmSIF_RTR_CTRL_2_E2E_PCI_RD_SIZE, 32);
1402 WREG32(mmSIF_RTR_CTRL_3_E2E_HBM_WR_SIZE, 176 >> 3);
1403 WREG32(mmSIF_RTR_CTRL_3_E2E_HBM_RD_SIZE, 32 >> 3);
1404 WREG32(mmSIF_RTR_CTRL_3_E2E_PCI_WR_SIZE, 19);
1405 WREG32(mmSIF_RTR_CTRL_3_E2E_PCI_RD_SIZE, 32);
1407 WREG32(mmSIF_RTR_CTRL_4_E2E_HBM_WR_SIZE, 176 >> 3);
1408 WREG32(mmSIF_RTR_CTRL_4_E2E_HBM_RD_SIZE, 32 >> 3);
1409 WREG32(mmSIF_RTR_CTRL_4_E2E_PCI_WR_SIZE, 19);
1410 WREG32(mmSIF_RTR_CTRL_4_E2E_PCI_RD_SIZE, 32);
1412 WREG32(mmSIF_RTR_CTRL_5_E2E_HBM_WR_SIZE, 1);
1413 WREG32(mmSIF_RTR_CTRL_5_E2E_HBM_RD_SIZE, 1);
1414 WREG32(mmSIF_RTR_CTRL_5_E2E_PCI_WR_SIZE, 1);
1415 WREG32(mmSIF_RTR_CTRL_5_E2E_PCI_RD_SIZE, 32);
1417 WREG32(mmSIF_RTR_CTRL_6_E2E_HBM_WR_SIZE, 275 >> 3);
1418 WREG32(mmSIF_RTR_CTRL_6_E2E_HBM_RD_SIZE, 614 >> 3);
1419 WREG32(mmSIF_RTR_CTRL_6_E2E_PCI_WR_SIZE, 1);
1420 WREG32(mmSIF_RTR_CTRL_6_E2E_PCI_RD_SIZE, 39);
1422 WREG32(mmSIF_RTR_CTRL_7_E2E_HBM_WR_SIZE, 297 >> 3);
1423 WREG32(mmSIF_RTR_CTRL_7_E2E_HBM_RD_SIZE, 908 >> 3);
1424 WREG32(mmSIF_RTR_CTRL_7_E2E_PCI_WR_SIZE, 19);
1425 WREG32(mmSIF_RTR_CTRL_7_E2E_PCI_RD_SIZE, 19);
1427 WREG32(mmNIF_RTR_CTRL_0_E2E_HBM_WR_SIZE, 318 >> 3);
1428 WREG32(mmNIF_RTR_CTRL_0_E2E_HBM_RD_SIZE, 956 >> 3);
1429 WREG32(mmNIF_RTR_CTRL_0_E2E_PCI_WR_SIZE, 79);
1430 WREG32(mmNIF_RTR_CTRL_0_E2E_PCI_RD_SIZE, 163);
1432 WREG32(mmNIF_RTR_CTRL_1_E2E_HBM_WR_SIZE, 275 >> 3);
1433 WREG32(mmNIF_RTR_CTRL_1_E2E_HBM_RD_SIZE, 614 >> 3);
1434 WREG32(mmNIF_RTR_CTRL_1_E2E_PCI_WR_SIZE, 1);
1435 WREG32(mmNIF_RTR_CTRL_1_E2E_PCI_RD_SIZE, 39);
1437 WREG32(mmNIF_RTR_CTRL_2_E2E_HBM_WR_SIZE, 1);
1438 WREG32(mmNIF_RTR_CTRL_2_E2E_HBM_RD_SIZE, 1);
1439 WREG32(mmNIF_RTR_CTRL_2_E2E_PCI_WR_SIZE, 1);
1440 WREG32(mmNIF_RTR_CTRL_2_E2E_PCI_RD_SIZE, 32);
1442 WREG32(mmNIF_RTR_CTRL_3_E2E_HBM_WR_SIZE, 176 >> 3);
1443 WREG32(mmNIF_RTR_CTRL_3_E2E_HBM_RD_SIZE, 32 >> 3);
1444 WREG32(mmNIF_RTR_CTRL_3_E2E_PCI_WR_SIZE, 19);
1445 WREG32(mmNIF_RTR_CTRL_3_E2E_PCI_RD_SIZE, 32);
1447 WREG32(mmNIF_RTR_CTRL_4_E2E_HBM_WR_SIZE, 176 >> 3);
1448 WREG32(mmNIF_RTR_CTRL_4_E2E_HBM_RD_SIZE, 32 >> 3);
1449 WREG32(mmNIF_RTR_CTRL_4_E2E_PCI_WR_SIZE, 19);
1450 WREG32(mmNIF_RTR_CTRL_4_E2E_PCI_RD_SIZE, 32);
1452 WREG32(mmNIF_RTR_CTRL_5_E2E_HBM_WR_SIZE, 1);
1453 WREG32(mmNIF_RTR_CTRL_5_E2E_HBM_RD_SIZE, 1);
1454 WREG32(mmNIF_RTR_CTRL_5_E2E_PCI_WR_SIZE, 1);
1455 WREG32(mmNIF_RTR_CTRL_5_E2E_PCI_RD_SIZE, 32);
1457 WREG32(mmNIF_RTR_CTRL_6_E2E_HBM_WR_SIZE, 275 >> 3);
1458 WREG32(mmNIF_RTR_CTRL_6_E2E_HBM_RD_SIZE, 614 >> 3);
1459 WREG32(mmNIF_RTR_CTRL_6_E2E_PCI_WR_SIZE, 1);
1460 WREG32(mmNIF_RTR_CTRL_6_E2E_PCI_RD_SIZE, 39);
1462 WREG32(mmNIF_RTR_CTRL_7_E2E_HBM_WR_SIZE, 318 >> 3);
1463 WREG32(mmNIF_RTR_CTRL_7_E2E_HBM_RD_SIZE, 956 >> 3);
1464 WREG32(mmNIF_RTR_CTRL_7_E2E_PCI_WR_SIZE, 79);
1465 WREG32(mmNIF_RTR_CTRL_7_E2E_PCI_RD_SIZE, 79);
1467 WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_WR_SIZE, 344 >> 3);
1468 WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_RD_SIZE, 1000 >> 3);
1469 WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_WR_SIZE, 162);
1470 WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_RD_SIZE, 338);
1472 WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_WR_SIZE, 344 >> 3);
1473 WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_RD_SIZE, 1000 >> 3);
1474 WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_WR_SIZE, 162);
1475 WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_RD_SIZE, 338);
1477 WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_WR_SIZE, 344 >> 3);
1478 WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_RD_SIZE, 1000 >> 3);
1479 WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_WR_SIZE, 162);
1480 WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_RD_SIZE, 338);
1482 WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_WR_SIZE, 344 >> 3);
1483 WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_RD_SIZE, 1000 >> 3);
1484 WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_WR_SIZE, 162);
1485 WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_RD_SIZE, 338);
1487 WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_WR_SIZE, 344 >> 3);
1488 WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_RD_SIZE, 1000 >> 3);
1489 WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_WR_SIZE, 162);
1490 WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_RD_SIZE, 338);
1492 WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_WR_SIZE, 344 >> 3);
1493 WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_RD_SIZE, 1000 >> 3);
1494 WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_WR_SIZE, 162);
1495 WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_RD_SIZE, 338);
1497 WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_WR_SIZE, 344 >> 3);
1498 WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_RD_SIZE, 1000 >> 3);
1499 WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_WR_SIZE, 162);
1500 WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_RD_SIZE, 338);
1502 WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_WR_SIZE, 344 >> 3);
1503 WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_RD_SIZE, 1000 >> 3);
1504 WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_WR_SIZE, 162);
1505 WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_RD_SIZE, 338);
1508 WREG32(mmSIF_RTR_CTRL_0_NL_HBM_SEL_0, 0x21);
1509 WREG32(mmSIF_RTR_CTRL_0_NL_HBM_SEL_1, 0x22);
1510 WREG32(mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_18, 0x1F);
1511 WREG32(mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_3, 0x20);
1513 WREG32(mmSIF_RTR_CTRL_1_NL_HBM_SEL_0, 0x21);
1514 WREG32(mmSIF_RTR_CTRL_1_NL_HBM_SEL_1, 0x22);
1515 WREG32(mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_18, 0x1F);
1516 WREG32(mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_3, 0x20);
1518 WREG32(mmSIF_RTR_CTRL_2_NL_HBM_SEL_0, 0x21);
1519 WREG32(mmSIF_RTR_CTRL_2_NL_HBM_SEL_1, 0x22);
1520 WREG32(mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_18, 0x1F);
1521 WREG32(mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_3, 0x20);
1523 WREG32(mmSIF_RTR_CTRL_3_NL_HBM_SEL_0, 0x21);
1524 WREG32(mmSIF_RTR_CTRL_3_NL_HBM_SEL_1, 0x22);
1525 WREG32(mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_18, 0x1F);
1526 WREG32(mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_3, 0x20);
1528 WREG32(mmSIF_RTR_CTRL_4_NL_HBM_SEL_0, 0x21);
1529 WREG32(mmSIF_RTR_CTRL_4_NL_HBM_SEL_1, 0x22);
1530 WREG32(mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_18, 0x1F);
1531 WREG32(mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_3, 0x20);
1533 WREG32(mmSIF_RTR_CTRL_5_NL_HBM_SEL_0, 0x21);
1534 WREG32(mmSIF_RTR_CTRL_5_NL_HBM_SEL_1, 0x22);
1535 WREG32(mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_18, 0x1F);
1536 WREG32(mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_3, 0x20);
1538 WREG32(mmSIF_RTR_CTRL_6_NL_HBM_SEL_0, 0x21);
1539 WREG32(mmSIF_RTR_CTRL_6_NL_HBM_SEL_1, 0x22);
1540 WREG32(mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_18, 0x1F);
1541 WREG32(mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_3, 0x20);
1543 WREG32(mmSIF_RTR_CTRL_7_NL_HBM_SEL_0, 0x21);
1544 WREG32(mmSIF_RTR_CTRL_7_NL_HBM_SEL_1, 0x22);
1545 WREG32(mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_18, 0x1F);
1546 WREG32(mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_3, 0x20);
1548 WREG32(mmNIF_RTR_CTRL_0_NL_HBM_SEL_0, 0x21);
1549 WREG32(mmNIF_RTR_CTRL_0_NL_HBM_SEL_1, 0x22);
1550 WREG32(mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_18, 0x1F);
1551 WREG32(mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_3, 0x20);
1553 WREG32(mmNIF_RTR_CTRL_1_NL_HBM_SEL_0, 0x21);
1554 WREG32(mmNIF_RTR_CTRL_1_NL_HBM_SEL_1, 0x22);
1555 WREG32(mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_18, 0x1F);
1556 WREG32(mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_3, 0x20);
1558 WREG32(mmNIF_RTR_CTRL_2_NL_HBM_SEL_0, 0x21);
1559 WREG32(mmNIF_RTR_CTRL_2_NL_HBM_SEL_1, 0x22);
1560 WREG32(mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_18, 0x1F);
1561 WREG32(mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_3, 0x20);
1563 WREG32(mmNIF_RTR_CTRL_3_NL_HBM_SEL_0, 0x21);
1564 WREG32(mmNIF_RTR_CTRL_3_NL_HBM_SEL_1, 0x22);
1565 WREG32(mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_18, 0x1F);
1566 WREG32(mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_3, 0x20);
1568 WREG32(mmNIF_RTR_CTRL_4_NL_HBM_SEL_0, 0x21);
1569 WREG32(mmNIF_RTR_CTRL_4_NL_HBM_SEL_1, 0x22);
1570 WREG32(mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_18, 0x1F);
1571 WREG32(mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_3, 0x20);
1573 WREG32(mmNIF_RTR_CTRL_5_NL_HBM_SEL_0, 0x21);
1574 WREG32(mmNIF_RTR_CTRL_5_NL_HBM_SEL_1, 0x22);
1575 WREG32(mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_18, 0x1F);
1576 WREG32(mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_3, 0x20);
1578 WREG32(mmNIF_RTR_CTRL_6_NL_HBM_SEL_0, 0x21);
1579 WREG32(mmNIF_RTR_CTRL_6_NL_HBM_SEL_1, 0x22);
1580 WREG32(mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_18, 0x1F);
1581 WREG32(mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_3, 0x20);
1583 WREG32(mmNIF_RTR_CTRL_7_NL_HBM_SEL_0, 0x21);
1584 WREG32(mmNIF_RTR_CTRL_7_NL_HBM_SEL_1, 0x22);
1585 WREG32(mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_18, 0x1F);
1586 WREG32(mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_3, 0x20);
1588 WREG32(mmDMA_IF_E_N_DOWN_CH0_NL_HBM_SEL_0, 0x21);
1589 WREG32(mmDMA_IF_E_N_DOWN_CH0_NL_HBM_SEL_1, 0x22);
1590 WREG32(mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_18, 0x1F);
1591 WREG32(mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_3, 0x20);
1593 WREG32(mmDMA_IF_E_N_DOWN_CH1_NL_HBM_SEL_0, 0x21);
1594 WREG32(mmDMA_IF_E_N_DOWN_CH1_NL_HBM_SEL_1, 0x22);
1595 WREG32(mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_18, 0x1F);
1596 WREG32(mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_3, 0x20);
1598 WREG32(mmDMA_IF_E_S_DOWN_CH0_NL_HBM_SEL_0, 0x21);
1599 WREG32(mmDMA_IF_E_S_DOWN_CH0_NL_HBM_SEL_1, 0x22);
1600 WREG32(mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_18, 0x1F);
1601 WREG32(mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_3, 0x20);
1603 WREG32(mmDMA_IF_E_S_DOWN_CH1_NL_HBM_SEL_0, 0x21);
1604 WREG32(mmDMA_IF_E_S_DOWN_CH1_NL_HBM_SEL_1, 0x22);
1605 WREG32(mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_18, 0x1F);
1606 WREG32(mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_3, 0x20);
1608 WREG32(mmDMA_IF_W_N_DOWN_CH0_NL_HBM_SEL_0, 0x21);
1609 WREG32(mmDMA_IF_W_N_DOWN_CH0_NL_HBM_SEL_1, 0x22);
1610 WREG32(mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_18, 0x1F);
1611 WREG32(mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_3, 0x20);
1613 WREG32(mmDMA_IF_W_N_DOWN_CH1_NL_HBM_SEL_0, 0x21);
1614 WREG32(mmDMA_IF_W_N_DOWN_CH1_NL_HBM_SEL_1, 0x22);
1615 WREG32(mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_18, 0x1F);
1616 WREG32(mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_3, 0x20);
1618 WREG32(mmDMA_IF_W_S_DOWN_CH0_NL_HBM_SEL_0, 0x21);
1619 WREG32(mmDMA_IF_W_S_DOWN_CH0_NL_HBM_SEL_1, 0x22);
1620 WREG32(mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_18, 0x1F);
1621 WREG32(mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_3, 0x20);
1623 WREG32(mmDMA_IF_W_S_DOWN_CH1_NL_HBM_SEL_0, 0x21);
1624 WREG32(mmDMA_IF_W_S_DOWN_CH1_NL_HBM_SEL_1, 0x22);
1625 WREG32(mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_18, 0x1F);
1626 WREG32(mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_3, 0x20);
1629 WREG32(mmSIF_RTR_CTRL_0_E2E_HBM_EN,
1631 WREG32(mmSIF_RTR_CTRL_0_E2E_PCI_EN,
1634 WREG32(mmSIF_RTR_CTRL_1_E2E_HBM_EN,
1636 WREG32(mmSIF_RTR_CTRL_1_E2E_PCI_EN,
1639 WREG32(mmSIF_RTR_CTRL_2_E2E_HBM_EN,
1641 WREG32(mmSIF_RTR_CTRL_2_E2E_PCI_EN,
1644 WREG32(mmSIF_RTR_CTRL_3_E2E_HBM_EN,
1646 WREG32(mmSIF_RTR_CTRL_3_E2E_PCI_EN,
1649 WREG32(mmSIF_RTR_CTRL_4_E2E_HBM_EN,
1651 WREG32(mmSIF_RTR_CTRL_4_E2E_PCI_EN,
1654 WREG32(mmSIF_RTR_CTRL_5_E2E_HBM_EN,
1656 WREG32(mmSIF_RTR_CTRL_5_E2E_PCI_EN,
1659 WREG32(mmSIF_RTR_CTRL_6_E2E_HBM_EN,
1661 WREG32(mmSIF_RTR_CTRL_6_E2E_PCI_EN,
1664 WREG32(mmSIF_RTR_CTRL_7_E2E_HBM_EN,
1666 WREG32(mmSIF_RTR_CTRL_7_E2E_PCI_EN,
1669 WREG32(mmNIF_RTR_CTRL_0_E2E_HBM_EN,
1671 WREG32(mmNIF_RTR_CTRL_0_E2E_PCI_EN,
1674 WREG32(mmNIF_RTR_CTRL_1_E2E_HBM_EN,
1676 WREG32(mmNIF_RTR_CTRL_1_E2E_PCI_EN,
1679 WREG32(mmNIF_RTR_CTRL_2_E2E_HBM_EN,
1681 WREG32(mmNIF_RTR_CTRL_2_E2E_PCI_EN,
1684 WREG32(mmNIF_RTR_CTRL_3_E2E_HBM_EN,
1686 WREG32(mmNIF_RTR_CTRL_3_E2E_PCI_EN,
1689 WREG32(mmNIF_RTR_CTRL_4_E2E_HBM_EN,
1691 WREG32(mmNIF_RTR_CTRL_4_E2E_PCI_EN,
1694 WREG32(mmNIF_RTR_CTRL_5_E2E_HBM_EN,
1696 WREG32(mmNIF_RTR_CTRL_5_E2E_PCI_EN,
1699 WREG32(mmNIF_RTR_CTRL_6_E2E_HBM_EN,
1701 WREG32(mmNIF_RTR_CTRL_6_E2E_PCI_EN,
1704 WREG32(mmNIF_RTR_CTRL_7_E2E_HBM_EN,
1706 WREG32(mmNIF_RTR_CTRL_7_E2E_PCI_EN,
1709 WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_EN,
1711 WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_EN,
1714 WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_EN,
1716 WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_EN,
1719 WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_EN,
1721 WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_EN,
1724 WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_EN,
1726 WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_EN,
1729 WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_EN,
1731 WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_EN,
1734 WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_EN,
1736 WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_EN,
1739 WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_EN,
1741 WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_EN,
1744 WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_EN,
1746 WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_EN,
1759 WREG32(mmDMA_IF_E_N_HBM0_WR_CRED_CNT, hbm0_wr);
1760 WREG32(mmDMA_IF_E_N_HBM1_WR_CRED_CNT, hbm1_wr);
1761 WREG32(mmDMA_IF_E_N_HBM0_RD_CRED_CNT, hbm0_rd);
1762 WREG32(mmDMA_IF_E_N_HBM1_RD_CRED_CNT, hbm1_rd);
1764 WREG32(mmDMA_IF_E_S_HBM0_WR_CRED_CNT, hbm0_wr);
1765 WREG32(mmDMA_IF_E_S_HBM1_WR_CRED_CNT, hbm1_wr);
1766 WREG32(mmDMA_IF_E_S_HBM0_RD_CRED_CNT, hbm0_rd);
1767 WREG32(mmDMA_IF_E_S_HBM1_RD_CRED_CNT, hbm1_rd);
1769 WREG32(mmDMA_IF_W_N_HBM0_WR_CRED_CNT, hbm0_wr);
1770 WREG32(mmDMA_IF_W_N_HBM1_WR_CRED_CNT, hbm1_wr);
1771 WREG32(mmDMA_IF_W_N_HBM0_RD_CRED_CNT, hbm0_rd);
1772 WREG32(mmDMA_IF_W_N_HBM1_RD_CRED_CNT, hbm1_rd);
1774 WREG32(mmDMA_IF_W_S_HBM0_WR_CRED_CNT, hbm0_wr);
1775 WREG32(mmDMA_IF_W_S_HBM1_WR_CRED_CNT, hbm1_wr);
1776 WREG32(mmDMA_IF_W_S_HBM0_RD_CRED_CNT, hbm0_rd);
1777 WREG32(mmDMA_IF_W_S_HBM1_RD_CRED_CNT, hbm1_rd);
1779 WREG32(mmDMA_IF_E_N_HBM_CRED_EN_0,
1782 WREG32(mmDMA_IF_E_S_HBM_CRED_EN_0,
1785 WREG32(mmDMA_IF_W_N_HBM_CRED_EN_0,
1788 WREG32(mmDMA_IF_W_S_HBM_CRED_EN_0,
1792 WREG32(mmDMA_IF_E_N_HBM_CRED_EN_1,
1795 WREG32(mmDMA_IF_E_S_HBM_CRED_EN_1,
1798 WREG32(mmDMA_IF_W_N_HBM_CRED_EN_1,
1801 WREG32(mmDMA_IF_W_S_HBM_CRED_EN_1,
1821 WREG32(mmTPC0_CFG_TPC_INTR_MASK + tpc_offset, 0x8FFF);
1831 WREG32(mmMME0_CTRL_EUS_ROLLUP_CNT_ADD, 3);
1832 WREG32(mmMME1_CTRL_EUS_ROLLUP_CNT_ADD, 3);
1833 WREG32(mmMME2_CTRL_EUS_ROLLUP_CNT_ADD, 3);
1834 WREG32(mmMME3_CTRL_EUS_ROLLUP_CNT_ADD, 3);
1866 WREG32(mmDMA0_QM_PQ_BASE_LO_0 + q_off, lower_32_bits(qman_pq_addr));
1867 WREG32(mmDMA0_QM_PQ_BASE_HI_0 + q_off, upper_32_bits(qman_pq_addr));
1869 WREG32(mmDMA0_QM_PQ_SIZE_0 + q_off, ilog2(HL_QUEUE_LENGTH));
1870 WREG32(mmDMA0_QM_PQ_PI_0 + q_off, 0);
1871 WREG32(mmDMA0_QM_PQ_CI_0 + q_off, 0);
1873 WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, QMAN_LDMA_SIZE_OFFSET);
1874 WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
1876 WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
1879 WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_en_lo);
1880 WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_en_hi);
1881 WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_en_lo);
1882 WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_en_hi);
1883 WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 + q_off, mtr_base_ws_lo);
1884 WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 + q_off, mtr_base_ws_hi);
1885 WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 + q_off, so_base_ws_lo);
1886 WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 + q_off, so_base_ws_hi);
1888 WREG32(mmDMA0_QM_CP_BARRIER_CFG_0 + q_off, 0x100);
1899 WREG32(mmDMA0_QM_GLBL_ERR_CFG + dma_qm_offset, dma_qm_err_cfg);
1900 WREG32(mmDMA0_QM_GLBL_ERR_ADDR_LO + dma_qm_offset,
1903 WREG32(mmDMA0_QM_GLBL_ERR_ADDR_HI + dma_qm_offset,
1906 WREG32(mmDMA0_QM_GLBL_ERR_WDATA + dma_qm_offset,
1910 WREG32(mmDMA0_QM_ARB_ERR_MSG_EN + dma_qm_offset,
1914 WREG32(mmDMA0_QM_ARB_SLV_CHOISE_WDT + dma_qm_offset,
1917 WREG32(mmDMA0_QM_GLBL_PROT + dma_qm_offset,
1920 WREG32(mmDMA0_QM_GLBL_CFG1 + dma_qm_offset, 0);
1930 WREG32(mmDMA0_CORE_RD_MAX_OUTSTAND + dma_offset, 0);
1931 WREG32(mmDMA0_CORE_RD_MAX_SIZE + dma_offset, 0);
1934 WREG32(mmDMA0_CORE_LBW_MAX_OUTSTAND + dma_offset, 15);
1940 WREG32(mmDMA0_CORE_ERR_CFG + dma_offset, dma_err_cfg);
1941 WREG32(mmDMA0_CORE_ERRMSG_ADDR_LO + dma_offset,
1943 WREG32(mmDMA0_CORE_ERRMSG_ADDR_HI + dma_offset,
1945 WREG32(mmDMA0_CORE_ERRMSG_WDATA + dma_offset,
1947 WREG32(mmDMA0_CORE_PROT + dma_offset,
1950 WREG32(mmDMA0_CORE_SECURE_PROPS + dma_offset,
1952 WREG32(mmDMA0_CORE_CFG_0 + dma_offset, 1 << DMA0_CORE_CFG_0_EN_SHIFT);
1960 WREG32(mmDMA0_QM_GLBL_CFG0 + dma_qm_offset, enable_mask);
2026 WREG32(mmDMA0_QM_PQ_BASE_LO_0 + q_off,
2028 WREG32(mmDMA0_QM_PQ_BASE_HI_0 + q_off,
2031 WREG32(mmDMA0_QM_PQ_SIZE_0 + q_off, ilog2(HBM_DMA_QMAN_LENGTH));
2032 WREG32(mmDMA0_QM_PQ_PI_0 + q_off, 0);
2033 WREG32(mmDMA0_QM_PQ_CI_0 + q_off, 0);
2035 WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
2037 WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
2039 WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
2042 WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
2044 WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
2046 WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
2055 WREG32(mmDMA0_QM_GLBL_ERR_CFG + dma_qm_offset, dma_qm_err_cfg);
2057 WREG32(mmDMA0_QM_GLBL_ERR_ADDR_LO + dma_qm_offset,
2060 WREG32(mmDMA0_QM_GLBL_ERR_ADDR_HI + dma_qm_offset,
2063 WREG32(mmDMA0_QM_GLBL_ERR_WDATA + dma_qm_offset,
2067 WREG32(mmDMA0_QM_ARB_ERR_MSG_EN + dma_qm_offset,
2071 WREG32(mmDMA0_QM_ARB_SLV_CHOISE_WDT + dma_qm_offset,
2074 WREG32(mmDMA0_QM_GLBL_CFG1 + dma_qm_offset, 0);
2075 WREG32(mmDMA0_QM_GLBL_PROT + dma_qm_offset,
2079 WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_lo);
2080 WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_hi);
2081 WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_lo);
2082 WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_hi);
2142 WREG32(mmMME0_QM_PQ_BASE_LO_0 + q_off,
2144 WREG32(mmMME0_QM_PQ_BASE_HI_0 + q_off,
2147 WREG32(mmMME0_QM_PQ_SIZE_0 + q_off, ilog2(MME_QMAN_LENGTH));
2148 WREG32(mmMME0_QM_PQ_PI_0 + q_off, 0);
2149 WREG32(mmMME0_QM_PQ_CI_0 + q_off, 0);
2151 WREG32(mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
2153 WREG32(mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
2155 WREG32(mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
2158 WREG32(mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
2160 WREG32(mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
2162 WREG32(mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
2174 WREG32(mmMME0_QM_GLBL_ERR_CFG + mme_offset, mme_qm_err_cfg);
2175 WREG32(mmMME0_QM_GLBL_ERR_ADDR_LO + mme_offset,
2178 WREG32(mmMME0_QM_GLBL_ERR_ADDR_HI + mme_offset,
2181 WREG32(mmMME0_QM_GLBL_ERR_WDATA + mme_offset,
2185 WREG32(mmMME0_QM_ARB_ERR_MSG_EN + mme_offset,
2189 WREG32(mmMME0_QM_ARB_SLV_CHOISE_WDT + mme_offset,
2192 WREG32(mmMME0_QM_GLBL_CFG1 + mme_offset, 0);
2193 WREG32(mmMME0_QM_GLBL_PROT + mme_offset,
2197 WREG32(mmMME0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_lo);
2198 WREG32(mmMME0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_hi);
2199 WREG32(mmMME0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_lo);
2200 WREG32(mmMME0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_hi);
2236 WREG32(mmMME2_QM_GLBL_CFG0, QMAN_MME_ENABLE);
2237 WREG32(mmMME0_QM_GLBL_CFG0, QMAN_MME_ENABLE);
2262 WREG32(mmTPC0_QM_PQ_BASE_LO_0 + q_off,
2264 WREG32(mmTPC0_QM_PQ_BASE_HI_0 + q_off,
2267 WREG32(mmTPC0_QM_PQ_SIZE_0 + q_off, ilog2(TPC_QMAN_LENGTH));
2268 WREG32(mmTPC0_QM_PQ_PI_0 + q_off, 0);
2269 WREG32(mmTPC0_QM_PQ_CI_0 + q_off, 0);
2271 WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
2273 WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
2275 WREG32(mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
2278 WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
2280 WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
2282 WREG32(mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
2295 WREG32(mmTPC0_QM_GLBL_ERR_CFG + tpc_offset, tpc_qm_err_cfg);
2296 WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + tpc_offset,
2299 WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + tpc_offset,
2302 WREG32(mmTPC0_QM_GLBL_ERR_WDATA + tpc_offset,
2306 WREG32(mmTPC0_QM_ARB_ERR_MSG_EN + tpc_offset,
2310 WREG32(mmTPC0_QM_ARB_SLV_CHOISE_WDT + tpc_offset,
2313 WREG32(mmTPC0_QM_GLBL_CFG1 + tpc_offset, 0);
2314 WREG32(mmTPC0_QM_GLBL_PROT + tpc_offset,
2318 WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_lo);
2319 WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_hi);
2320 WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_lo);
2321 WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_hi);
2354 WREG32(mmTPC0_QM_GLBL_CFG0 + tpc_offset,
2359 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_HIGH + tpc_id * tpc_delta,
2376 WREG32(mmDMA0_QM_GLBL_CFG0, 0);
2377 WREG32(mmDMA1_QM_GLBL_CFG0, 0);
2378 WREG32(mmDMA5_QM_GLBL_CFG0, 0);
2388 WREG32(mmDMA2_QM_GLBL_CFG0, 0);
2389 WREG32(mmDMA3_QM_GLBL_CFG0, 0);
2390 WREG32(mmDMA4_QM_GLBL_CFG0, 0);
2391 WREG32(mmDMA6_QM_GLBL_CFG0, 0);
2392 WREG32(mmDMA7_QM_GLBL_CFG0, 0);
2402 WREG32(mmMME2_QM_GLBL_CFG0, 0);
2403 WREG32(mmMME0_QM_GLBL_CFG0, 0);
2416 WREG32(mmTPC0_QM_GLBL_CFG0 + tpc_offset, 0);
2429 WREG32(mmDMA0_QM_GLBL_CFG1, 0xF << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
2430 WREG32(mmDMA1_QM_GLBL_CFG1, 0xF << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
2431 WREG32(mmDMA5_QM_GLBL_CFG1, 0xF << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
2443 WREG32(mmDMA2_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
2444 WREG32(mmDMA3_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
2445 WREG32(mmDMA4_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
2446 WREG32(mmDMA6_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
2447 WREG32(mmDMA7_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
2458 WREG32(mmMME2_QM_GLBL_CFG1, 0x1F << MME0_QM_GLBL_CFG1_CP_STOP_SHIFT);
2459 WREG32(mmMME0_QM_GLBL_CFG1, 0x1F << MME0_QM_GLBL_CFG1_CP_STOP_SHIFT);
2469 WREG32(mmTPC0_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
2470 WREG32(mmTPC1_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
2471 WREG32(mmTPC2_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
2472 WREG32(mmTPC3_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
2473 WREG32(mmTPC4_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
2474 WREG32(mmTPC5_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
2475 WREG32(mmTPC6_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
2476 WREG32(mmTPC7_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
2486 WREG32(mmDMA0_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
2487 WREG32(mmDMA1_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
2488 WREG32(mmDMA5_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
2498 WREG32(mmDMA2_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
2499 WREG32(mmDMA3_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
2500 WREG32(mmDMA4_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
2501 WREG32(mmDMA6_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
2502 WREG32(mmDMA7_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
2513 WREG32(mmMME0_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
2514 WREG32(mmMME0_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
2515 WREG32(mmMME0_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
2516 WREG32(mmMME0_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
2517 WREG32(mmMME1_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
2518 WREG32(mmMME1_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
2519 WREG32(mmMME1_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
2520 WREG32(mmMME1_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
2521 WREG32(mmMME2_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
2522 WREG32(mmMME2_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
2523 WREG32(mmMME2_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
2524 WREG32(mmMME2_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
2525 WREG32(mmMME3_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
2526 WREG32(mmMME3_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
2527 WREG32(mmMME3_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
2528 WREG32(mmMME3_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
2538 WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
2539 WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
2540 WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
2541 WREG32(mmTPC3_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
2542 WREG32(mmTPC4_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
2543 WREG32(mmTPC5_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
2544 WREG32(mmTPC6_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
2545 WREG32(mmTPC7_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
2566 WREG32(mmDMA0_QM_CGM_CFG1 + qman_offset,
2568 WREG32(mmDMA0_QM_CGM_CFG + qman_offset,
2577 WREG32(mmDMA0_QM_CGM_CFG1 + qman_offset,
2579 WREG32(mmDMA0_QM_CGM_CFG + qman_offset,
2584 WREG32(mmMME0_QM_CGM_CFG1, enable ? QMAN_CGM1_PWR_GATE_EN : 0);
2585 WREG32(mmMME0_QM_CGM_CFG, enable ? QMAN_COMMON_CP_CGM_PWR_GATE_EN : 0);
2588 WREG32(mmMME2_QM_CGM_CFG1, enable ? QMAN_CGM1_PWR_GATE_EN : 0);
2589 WREG32(mmMME2_QM_CGM_CFG, enable ? QMAN_COMMON_CP_CGM_PWR_GATE_EN : 0);
2595 WREG32(mmTPC0_QM_CGM_CFG1 + qman_offset,
2597 WREG32(mmTPC0_QM_CGM_CFG + qman_offset,
2616 WREG32(mmDMA0_QM_CGM_CFG + qman_offset, 0);
2617 WREG32(mmDMA0_QM_CGM_CFG1 + qman_offset, 0);
2622 WREG32(mmMME0_QM_CGM_CFG, 0);
2623 WREG32(mmMME0_QM_CGM_CFG1, 0);
2624 WREG32(mmMME2_QM_CGM_CFG, 0);
2625 WREG32(mmMME2_QM_CGM_CFG1, 0);
2628 WREG32(mmTPC0_QM_CGM_CFG + qman_offset, 0);
2629 WREG32(mmTPC0_QM_CGM_CFG1 + qman_offset, 0);
2640 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
2643 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0xC, 0);
2644 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0x8, 0);
2647 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 1);
2653 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
2723 WREG32(mmSTLB_CACHE_INV_BASE_39_8, MMU_CACHE_MNG_ADDR >> 8);
2724 WREG32(mmSTLB_CACHE_INV_BASE_49_40, MMU_CACHE_MNG_ADDR >> 40);
2728 WREG32(mmMMU_UP_MMU_ENABLE, 1);
2729 WREG32(mmMMU_UP_SPI_MASK, 0xF);
2731 WREG32(mmSTLB_HOP_CONFIGURATION,
2819 WREG32(mmCPU_IF_CPU_MSB_ADDR, hdev->cpu_pci_msb_addr);
2853 WREG32(mmCPU_IF_PQ_BASE_ADDR_LOW, lower_32_bits(cpu_pq->bus_address));
2854 WREG32(mmCPU_IF_PQ_BASE_ADDR_HIGH, upper_32_bits(cpu_pq->bus_address));
2856 WREG32(mmCPU_IF_EQ_BASE_ADDR_LOW, lower_32_bits(eq->bus_address));
2857 WREG32(mmCPU_IF_EQ_BASE_ADDR_HIGH, upper_32_bits(eq->bus_address));
2859 WREG32(mmCPU_IF_CQ_BASE_ADDR_LOW,
2861 WREG32(mmCPU_IF_CQ_BASE_ADDR_HIGH,
2864 WREG32(mmCPU_IF_PQ_LENGTH, HL_QUEUE_SIZE_IN_BYTES);
2865 WREG32(mmCPU_IF_EQ_LENGTH, HL_EQ_SIZE_IN_BYTES);
2866 WREG32(mmCPU_IF_CQ_LENGTH, HL_CPU_ACCESSIBLE_MEM_SIZE);
2869 WREG32(mmCPU_IF_EQ_RD_OFFS, 0);
2871 WREG32(mmCPU_IF_PF_PQ_PI, 0);
2874 WREG32(mmCPU_IF_QUEUE_INIT, PQ_INIT_STATUS_READY_FOR_CP);
2876 WREG32(mmCPU_IF_QUEUE_INIT,
2879 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, GAUDI_EVENT_PI_UPDATE);
2907 WREG32(mmPCIE_WRAP_LBW_PROT_OVR,
2922 WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY);
2927 WREG32(mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_H,
2933 WREG32(mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_L, CFG_RST_L_TPC_MASK);
2935 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H,
2945 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L,
3039 WREG32(mmPCIE_AUX_FLR_CTRL, (PCIE_AUX_FLR_CTRL_HW_CTRL_MASK |
3045 WREG32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU, KMD_MSG_GOTO_WFE);
3046 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, GAUDI_EVENT_HALT_MACHINE);
3051 WREG32(mmPREBOOT_PCIE_EN, LKD_HARD_RESET_MAGIC);
3061 WREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS, boot_strap & ~0x2);
3064 WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START, 1);
3066 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST,
3084 WREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS, boot_strap);
3375 WREG32(db_reg_offset, db_value);
3378 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
4332 WREG32(mmCPU_IF_EQ_RD_OFFS, val);
4376 WREG32(mmDMA0_CORE_ERR_CAUSE, err_cause);
4403 WREG32(mmDMA0_CORE_ERR_CAUSE, err_cause);
4419 WREG32(mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0 + i, 0);
4420 WREG32(mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_SOB_OBJ_0 + i, 0);
4421 WREG32(mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_SOB_OBJ_0 + i, 0);
4425 WREG32(mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0 + i, 0);
4426 WREG32(mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_MON_STATUS_0 + i, 0);
4427 WREG32(mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_MON_STATUS_0 + i, 0);
4433 WREG32(mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 + i, 0);
4438 WREG32(mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0 + i, 0);
4453 WREG32(mmDMA0_CORE_WR_COMP_ADDR_LO + dma_offset,
4455 WREG32(mmDMA0_CORE_WR_COMP_ADDR_HI + dma_offset,
4457 WREG32(mmDMA0_CORE_WR_COMP_WDATA + dma_offset, 0x80000001);
4463 WREG32(mmDMA0_CORE_WR_AWUSER_31_11 + dma_offset,
4475 WREG32(mmDMA0_QM_ARB_CFG_0 + qman_offset, 0);
4480 WREG32(mmMME0_QM_ARB_CFG_0 + qman_offset, 0);
4485 WREG32(mmTPC0_QM_ARB_CFG_0 + qman_offset, 0);
4600 WREG32(addr - CFG_BASE, val);
4698 WREG32(addr - CFG_BASE, lower_32_bits(val));
4699 WREG32(addr + sizeof(u32) - CFG_BASE,
5187 WREG32(mmMMU_UP_RAZWI_WRITE_VLD, 0);
5194 WREG32(mmMMU_UP_RAZWI_READ_VLD, 0);
5216 WREG32(mmMMU_UP_PAGE_ERROR_CAPTURE, 0);
5228 WREG32(mmMMU_UP_ACCESS_ERROR_CAPTURE, 0);
5295 WREG32(params->block_address + GAUDI_ECC_MEM_SEL_OFFSET,
5310 WREG32(params->block_address + GAUDI_ECC_MEM_INFO_CLR_OFFSET, reg);
5354 WREG32(glbl_sts_addr + 4 * i, glbl_sts_clr_val);
5582 WREG32(base + (ch * 0x1000) + 0x06C, 0x1F1F);
5583 WREG32(base + (ch * 0x1000) + 0x07C, 0x1F1F);
5662 WREG32(mmTPC0_CFG_TPC_INTR_CAUSE + tpc_offset, 0);
5960 WREG32(mmSTLB_INV_PS, 3);
5961 WREG32(mmSTLB_CACHE_INV, gaudi->mmu_cache_inv_pi++);
5962 WREG32(mmSTLB_INV_PS, 2);
5972 WREG32(mmSTLB_INV_SET, 0);
6016 WREG32(mmSTLB_CACHE_INV,
6049 WREG32(MMU_ASID, asid);
6050 WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT);
6051 WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT);
6052 WREG32(MMU_BUSY, 0x80000000);
6273 WREG32(mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW + offset,
6275 WREG32(mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH + offset,
6278 WREG32(mmTPC0_CFG_ICACHE_BASE_ADDERESS_LOW + offset,
6280 WREG32(mmTPC0_CFG_ICACHE_BASE_ADDERESS_HIGH + offset,
6283 WREG32(mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_LO + offset,
6285 WREG32(mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_HI + offset,
6288 WREG32(mmTPC0_CFG_QM_SYNC_OBJECT_ADDR + offset,
6292 WREG32(mmTPC0_CFG_TPC_CMD + offset,
6317 WREG32(mmTPC0_CFG_TPC_EXECUTE + offset,
6590 WREG32(mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 + hw_sob->sob_id * 4,