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/kernel/linux/linux-6.6/drivers/iio/health/
H A Dafe4404.c198 int val, integer, fract, ret; in afe440x_store_register() local
204 for (val = 0; val < afe440x_attr->table_size; val++) in afe440x_store_register()
205 if (afe440x_attr->val_table[val].integer == integer && in afe440x_store_register()
206 afe440x_attr->val_table[val].fract == fract) in afe440x_store_register()
208 if (val == afe440x_attr->table_size) in afe440x_store_register()
211 ret = regmap_field_write(afe->fields[afe440x_attr->field], val); in afe440x_store_register()
250 int *val, int *val2, long mask) in afe4404_read_raw()
261 ret = regmap_read(afe->regmap, value_reg, val); in afe4404_read_raw()
248 afe4404_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) afe4404_read_raw() argument
294 afe4404_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) afe4404_write_raw() argument
[all...]
H A Dafe4403.c167 int val, integer, fract, ret; in afe440x_store_register() local
173 for (val = 0; val < afe440x_attr->table_size; val++) in afe440x_store_register()
174 if (afe440x_attr->val_table[val].integer == integer && in afe440x_store_register()
175 afe440x_attr->val_table[val].fract == fract) in afe440x_store_register()
177 if (val == afe440x_attr->table_size) in afe440x_store_register()
180 ret = regmap_field_write(afe->fields[afe440x_attr->field], val); in afe440x_store_register()
217 static int afe4403_read(struct afe4403_data *afe, unsigned int reg, u32 *val) in afe4403_read() argument
232 *val in afe4403_read()
243 afe4403_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) afe4403_read_raw() argument
283 afe4403_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) afe4403_write_raw() argument
[all...]
/kernel/linux/linux-6.6/rust/kernel/
H A Dinit.rs273 (let $var:ident $(: $t:ty)? = $val:expr) => {
274 let val = $val;
276 let mut $var = match $crate::init::__internal::StackInit::init($var, val) {
349 (let $var:ident $(: $t:ty)? = $val:expr) => {
350 let val = $val;
352 let mut $var = $crate::init::__internal::StackInit::init($var, val);
354 (let $var:ident $(: $t:ty)? =? $val:expr) => {
355 let val
[all...]
/kernel/linux/linux-6.6/tools/perf/util/
H A Dperf_event_attr_fprintf.c242 #define p_hex(val) snprintf(buf, BUF_SIZE, "%#"PRIx64, (uint64_t)(val))
243 #define p_unsigned(val) snprintf(buf, BUF_SIZE, "%"PRIu64, (uint64_t)(val))
244 #define p_signed(val) snprintf(buf, BUF_SIZE, "%"PRId64, (int64_t)(val))
245 #define p_sample_type(val) __p_sample_type(buf, BUF_SIZE, val)
246 #define p_branch_sample_type(val) __p_branch_sample_type(buf, BUF_SIZE, val)
[all...]
/kernel/linux/linux-5.10/drivers/perf/
H A Dxgene_pmu.c107 void (*write_counter)(struct xgene_pmu_dev *pmu, int idx, u64 val);
108 void (*write_evttype)(struct xgene_pmu_dev *pmu_dev, int idx, u32 val);
109 void (*write_agentmsk)(struct xgene_pmu_dev *pmu_dev, u32 val);
110 void (*write_agent1msk)(struct xgene_pmu_dev *pmu_dev, u32 val);
760 xgene_pmu_write_counter32(struct xgene_pmu_dev *pmu_dev, int idx, u64 val) in xgene_pmu_write_counter32() argument
762 writel(val, pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx)); in xgene_pmu_write_counter32()
766 xgene_pmu_write_counter64(struct xgene_pmu_dev *pmu_dev, int idx, u64 val) in xgene_pmu_write_counter64() argument
770 cnt_hi = upper_32_bits(val); in xgene_pmu_write_counter64()
771 cnt_lo = lower_32_bits(val); in xgene_pmu_write_counter64()
779 xgene_pmu_write_evttype(struct xgene_pmu_dev *pmu_dev, int idx, u32 val) in xgene_pmu_write_evttype() argument
785 xgene_pmu_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val) xgene_pmu_write_agentmsk() argument
791 xgene_pmu_v3_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val) xgene_pmu_v3_write_agentmsk() argument
794 xgene_pmu_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val) xgene_pmu_write_agent1msk() argument
800 xgene_pmu_v3_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val) xgene_pmu_v3_write_agent1msk() argument
805 u32 val; xgene_pmu_enable_counter() local
815 u32 val; xgene_pmu_disable_counter() local
825 u32 val; xgene_pmu_enable_counter_int() local
835 u32 val; xgene_pmu_disable_counter_int() local
844 u32 val; xgene_pmu_reset_counters() local
853 u32 val; xgene_pmu_start_counters() local
862 u32 val; xgene_pmu_stop_counters() local
984 u64 val = 1ULL << 31; xgene_perf_event_set_period() local
1238 u32 val; xgene_pmu_isr() local
[all...]
/kernel/linux/linux-5.10/drivers/soc/qcom/
H A Dcpr.c270 u32 val; in cpr_masked_write() local
272 val = readl_relaxed(drv->base + offset); in cpr_masked_write()
273 val &= ~mask; in cpr_masked_write()
274 val |= value & mask; in cpr_masked_write()
275 writel_relaxed(val, drv->base + offset); in cpr_masked_write()
307 u32 val, mask; in cpr_ctl_enable() local
311 val = desc->timer_cons_down << RBIF_TIMER_ADJ_CONS_DOWN_SHIFT; in cpr_ctl_enable()
312 val |= desc->timer_cons_up << RBIF_TIMER_ADJ_CONS_UP_SHIFT; in cpr_ctl_enable()
314 cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST, mask, val); in cpr_ctl_enable()
322 val in cpr_ctl_enable()
463 u32 val, error_steps, reg_mask; cpr_scale() local
594 u32 val; cpr_irq_handler() local
683 u32 val, gcnt; cpr_config() local
[all...]
/kernel/linux/linux-6.6/drivers/pmdomain/qcom/
H A Dcpr.c269 u32 val; in cpr_masked_write() local
271 val = readl_relaxed(drv->base + offset); in cpr_masked_write()
272 val &= ~mask; in cpr_masked_write()
273 val |= value & mask; in cpr_masked_write()
274 writel_relaxed(val, drv->base + offset); in cpr_masked_write()
306 u32 val, mask; in cpr_ctl_enable() local
310 val = desc->timer_cons_down << RBIF_TIMER_ADJ_CONS_DOWN_SHIFT; in cpr_ctl_enable()
311 val |= desc->timer_cons_up << RBIF_TIMER_ADJ_CONS_UP_SHIFT; in cpr_ctl_enable()
313 cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST, mask, val); in cpr_ctl_enable()
321 val in cpr_ctl_enable()
462 u32 val, error_steps, reg_mask; cpr_scale() local
593 u32 val; cpr_irq_handler() local
682 u32 val, gcnt; cpr_config() local
[all...]
/kernel/linux/linux-6.6/drivers/ptp/
H A Dptp_clockmatrix.c246 u8 val = 0; in arm_tod_read_trig_sel_refclk() local
249 val &= ~(WR_REF_INDEX_MASK << WR_REF_INDEX_SHIFT); in arm_tod_read_trig_sel_refclk()
250 val |= (ref << WR_REF_INDEX_SHIFT); in arm_tod_read_trig_sel_refclk()
253 TOD_READ_SECONDARY_SEL_CFG_0, &val, sizeof(val)); in arm_tod_read_trig_sel_refclk()
257 val = 0 | (SCSR_TOD_READ_TRIG_SEL_REFCLK << TOD_READ_TRIGGER_SHIFT); in arm_tod_read_trig_sel_refclk()
260 &val, sizeof(val)); in arm_tod_read_trig_sel_refclk()
490 u8 val = (SCSR_TOD_READ_TRIG_SEL_IMMEDIATE << TOD_READ_TRIGGER_SHIFT); in _idtcm_gettime_immediate() local
494 tod_read_cmd, &val, sizeo in _idtcm_gettime_immediate()
508 u8 val; _sync_pll_output() local
1146 set_pll_output_mask(struct idtcm *idtcm, u16 addr, u8 val) set_pll_output_mask() argument
1200 check_and_set_masks(struct idtcm *idtcm, u16 regaddr, u8 val) check_and_set_masks() argument
1263 u8 val; idtcm_load_firmware() local
1333 u8 val; idtcm_output_enable() local
[all...]
/kernel/linux/linux-6.6/drivers/clk/
H A Dclk-si5351.c85 u32 val; in si5351_reg_read() local
88 ret = regmap_read(drvdata->regmap, reg, &val); in si5351_reg_read()
95 return (u8)val; in si5351_reg_read()
105 u8 reg, u8 val) in si5351_reg_write()
107 return regmap_write(drvdata->regmap, reg, val); in si5351_reg_write()
117 u8 reg, u8 mask, u8 val) in si5351_set_bits()
119 return regmap_update_bits(drvdata->regmap, reg, mask, val); in si5351_set_bits()
390 u8 val; in si5351_pll_get_parent() local
392 val = si5351_reg_read(hwdata->drvdata, SI5351_PLL_INPUT_SOURCE); in si5351_pll_get_parent()
394 return (val in si5351_pll_get_parent()
104 si5351_reg_write(struct si5351_driver_data *drvdata, u8 reg, u8 val) si5351_reg_write() argument
116 si5351_set_bits(struct si5351_driver_data *drvdata, u8 reg, u8 mask, u8 val) si5351_set_bits() argument
584 u8 val; si5351_msynth_get_parent() local
807 u8 val; _si5351_clkout_reparent() local
880 u8 val; _si5351_clkout_set_disable_state() local
909 u8 val = si5351_reg_read(drvdata, SI5351_CLK0_CTRL + num); _si5351_clkout_reset_pll() local
971 unsigned char val; si5351_clkout_get_parent() local
1178 u32 val; si5351_dt_parse() local
[all...]
/kernel/linux/linux-6.6/drivers/perf/
H A Dxgene_pmu.c107 void (*write_counter)(struct xgene_pmu_dev *pmu, int idx, u64 val);
108 void (*write_evttype)(struct xgene_pmu_dev *pmu_dev, int idx, u32 val);
109 void (*write_agentmsk)(struct xgene_pmu_dev *pmu_dev, u32 val);
110 void (*write_agent1msk)(struct xgene_pmu_dev *pmu_dev, u32 val);
757 xgene_pmu_write_counter32(struct xgene_pmu_dev *pmu_dev, int idx, u64 val) in xgene_pmu_write_counter32() argument
759 writel(val, pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx)); in xgene_pmu_write_counter32()
763 xgene_pmu_write_counter64(struct xgene_pmu_dev *pmu_dev, int idx, u64 val) in xgene_pmu_write_counter64() argument
767 cnt_hi = upper_32_bits(val); in xgene_pmu_write_counter64()
768 cnt_lo = lower_32_bits(val); in xgene_pmu_write_counter64()
776 xgene_pmu_write_evttype(struct xgene_pmu_dev *pmu_dev, int idx, u32 val) in xgene_pmu_write_evttype() argument
782 xgene_pmu_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val) xgene_pmu_write_agentmsk() argument
788 xgene_pmu_v3_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val) xgene_pmu_v3_write_agentmsk() argument
791 xgene_pmu_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val) xgene_pmu_write_agent1msk() argument
797 xgene_pmu_v3_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val) xgene_pmu_v3_write_agent1msk() argument
802 u32 val; xgene_pmu_enable_counter() local
812 u32 val; xgene_pmu_disable_counter() local
822 u32 val; xgene_pmu_enable_counter_int() local
832 u32 val; xgene_pmu_disable_counter_int() local
841 u32 val; xgene_pmu_reset_counters() local
850 u32 val; xgene_pmu_start_counters() local
859 u32 val; xgene_pmu_stop_counters() local
981 u64 val = 1ULL << 31; xgene_perf_event_set_period() local
1234 u32 val; xgene_pmu_isr() local
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_panel.c515 u32 val) in intel_panel_compute_brightness()
523 return val; in intel_panel_compute_brightness()
527 return panel->backlight.max - val + panel->backlight.min; in intel_panel_compute_brightness()
530 return val; in intel_panel_compute_brightness()
551 u32 val; in i9xx_get_backlight() local
553 val = intel_de_read(dev_priv, BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in i9xx_get_backlight()
555 val >>= 1; in i9xx_get_backlight()
561 val *= lbpc; in i9xx_get_backlight()
564 return val; in i9xx_get_backlight()
606 u32 val in lpt_set_backlight() local
514 intel_panel_compute_brightness(struct intel_connector *connector, u32 val) intel_panel_compute_brightness() argument
807 u32 tmp, val; bxt_disable_backlight() local
1088 u32 pwm_ctl, val; bxt_enable_backlight() local
1232 u32 val = 0; intel_panel_get_backlight() local
1619 u32 cpu_ctl2, pch_ctl1, pch_ctl2, val; lpt_setup_backlight() local
1678 u32 cpu_ctl2, pch_ctl1, pch_ctl2, val; pch_setup_backlight() local
1710 u32 ctl, val; i9xx_setup_backlight() local
1749 u32 ctl, ctl2, val; i965_setup_backlight() local
1783 u32 ctl, ctl2, val; vlv_setup_backlight() local
1817 u32 pwm_ctl, val; bxt_setup_backlight() local
1859 u32 pwm_ctl, val; cnp_setup_backlight() local
[all...]
/kernel/linux/linux-6.6/drivers/input/misc/
H A Diqs7222.c142 u16 val; member
166 .val = BIT(0),
173 .val = BIT(1),
180 .val = BIT(5) | BIT(1),
187 .val = BIT(2),
194 .val = BIT(5) | BIT(2),
209 .val = BIT(0),
217 .val = BIT(2),
226 .val = BIT(3),
235 .val
1606 iqs7222_read_burst(struct iqs7222_private *iqs7222, u16 reg, void *val, u16 num_val) iqs7222_read_burst() argument
1673 iqs7222_read_word(struct iqs7222_private *iqs7222, u16 reg, u16 *val) iqs7222_read_word() argument
1687 iqs7222_write_burst(struct iqs7222_private *iqs7222, u16 reg, const void *val, u16 num_val) iqs7222_write_burst() argument
1746 iqs7222_write_word(struct iqs7222_private *iqs7222, u16 reg, u16 val) iqs7222_write_word() argument
1886 u16 *val; iqs7222_dev_init() local
2080 unsigned int val; iqs7222_parse_props() local
2257 unsigned int val; iqs7222_parse_chan() local
2461 unsigned int chan_sel[4], val; iqs7222_parse_sldr() local
2995 u16 val = iqs7222_sl_events[j].val; iqs7222_report() local
3030 u16 val = iqs7222_tp_events[j].val; iqs7222_report() local
[all...]
/kernel/linux/linux-5.10/arch/powerpc/kvm/
H A Dbook3s_hv.c1659 union kvmppc_one_reg *val) in kvmppc_get_one_reg_hv()
1666 *val = get_reg_val(id, KVMPPC_INST_SW_BREAKPOINT); in kvmppc_get_one_reg_hv()
1669 *val = get_reg_val(id, 0); in kvmppc_get_one_reg_hv()
1672 *val = get_reg_val(id, vcpu->arch.dabr); in kvmppc_get_one_reg_hv()
1675 *val = get_reg_val(id, vcpu->arch.dabrx); in kvmppc_get_one_reg_hv()
1678 *val = get_reg_val(id, vcpu->arch.dscr); in kvmppc_get_one_reg_hv()
1681 *val = get_reg_val(id, vcpu->arch.purr); in kvmppc_get_one_reg_hv()
1684 *val = get_reg_val(id, vcpu->arch.spurr); in kvmppc_get_one_reg_hv()
1687 *val = get_reg_val(id, vcpu->arch.amr); in kvmppc_get_one_reg_hv()
1690 *val in kvmppc_get_one_reg_hv()
1658 kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id, union kvmppc_one_reg *val) kvmppc_get_one_reg_hv() argument
1897 kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id, union kvmppc_one_reg *val) kvmppc_set_one_reg_hv() argument
[all...]
H A Dmpic.c125 u32 val, int idx);
129 uint32_t val);
580 uint32_t val) in write_IRQreg_idr()
594 src->idr = val & mask; in write_IRQreg_idr()
625 uint32_t val) in write_IRQreg_ilr()
630 src->output = val & ILR_INTTGT_MASK; in write_IRQreg_ilr()
639 uint32_t val) in write_IRQreg_ivpr()
651 (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask); in write_IRQreg_ivpr()
673 pr_debug("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ, val, in write_IRQreg_ivpr()
677 static void openpic_gcr_write(struct openpic *opp, uint64_t val) in openpic_gcr_write() argument
579 write_IRQreg_idr(struct openpic *opp, int n_IRQ, uint32_t val) write_IRQreg_idr() argument
624 write_IRQreg_ilr(struct openpic *opp, int n_IRQ, uint32_t val) write_IRQreg_ilr() argument
638 write_IRQreg_ivpr(struct openpic *opp, int n_IRQ, uint32_t val) write_IRQreg_ivpr() argument
688 openpic_gbl_write(void *opaque, gpa_t addr, u32 val) openpic_gbl_write() argument
806 openpic_tmr_write(void *opaque, gpa_t addr, u32 val) openpic_tmr_write() argument
886 openpic_src_write(void *opaque, gpa_t addr, u32 val) openpic_src_write() argument
940 openpic_msi_write(void *opaque, gpa_t addr, u32 val) openpic_msi_write() argument
1015 openpic_summary_write(void *opaque, gpa_t addr, u32 val) openpic_summary_write() argument
1023 openpic_cpu_write_internal(void *opaque, gpa_t addr, u32 val, int idx) openpic_cpu_write_internal() argument
1118 openpic_cpu_write(void *opaque, gpa_t addr, u32 val) openpic_cpu_write() argument
1355 kvm_mpic_write_internal(struct openpic *opp, gpa_t addr, u32 val) kvm_mpic_write_internal() argument
1378 u32 val; kvm_mpic_read() member
1496 access_reg(struct openpic *opp, gpa_t addr, u32 *val, int type) access_reg() argument
[all...]
/kernel/linux/linux-5.10/drivers/net/wireless/ath/ath10k/
H A Dpci.c432 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + in ath10k_pci_is_awake() local
435 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON; in ath10k_pci_is_awake()
654 u32 val; in ath10k_bus_pci_read32() local
657 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) { in ath10k_bus_pci_read32()
659 offset, offset + sizeof(val), ar_pci->mem_len); in ath10k_bus_pci_read32()
670 val = ioread32(ar_pci->mem + offset); in ath10k_bus_pci_read32()
673 return val; in ath10k_bus_pci_read32()
695 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val) in ath10k_pci_soc_write32() argument
697 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val); in ath10k_pci_soc_write32()
705 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val) in ath10k_pci_reg_write32() argument
854 u32 val = 0, region = addr & 0xfffff; ath10k_pci_qca988x_targ_cpu_to_ce_addr() local
869 u32 val = 0, region = addr & 0xfffff; ath10k_pci_qca6174_targ_cpu_to_ce_addr() local
879 u32 val = 0, region = addr & 0xfffff; ath10k_pci_qca99x0_targ_cpu_to_ce_addr() local
1010 __le32 val = 0; ath10k_pci_diag_read32() local
1165 __le32 val = __cpu_to_le32(value); ath10k_pci_diag_write32() local
1565 u32 val; ath10k_pci_set_ram_config() local
1880 u32 val; ath10k_pci_irq_msi_fw_mask() local
1908 u32 val; ath10k_pci_irq_msi_fw_unmask() local
2268 u32 addr, val; ath10k_pci_wake_target_cpu() local
2552 u32 val; ath10k_pci_fw_crashed_clear() local
2561 u32 val; ath10k_pci_has_device_gone() local
2570 u32 val; ath10k_pci_warm_reset_si0() local
2589 u32 val; ath10k_pci_warm_reset_cpu() local
2600 u32 val; ath10k_pci_warm_reset_ce() local
2613 u32 val; ath10k_pci_warm_reset_clear_lf() local
2677 u32 val; ath10k_pci_qca988x_chip_reset() local
2913 u32 val; ath10k_pci_resume() local
3286 u32 val; ath10k_pci_wait_for_target_init() local
3341 u32 val; ath10k_pci_cold_reset() local
[all...]
/kernel/linux/linux-6.6/drivers/net/wireless/ath/ath10k/
H A Dpci.c432 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + in ath10k_pci_is_awake() local
435 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON; in ath10k_pci_is_awake()
654 u32 val; in ath10k_bus_pci_read32() local
657 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) { in ath10k_bus_pci_read32()
659 offset, offset + sizeof(val), ar_pci->mem_len); in ath10k_bus_pci_read32()
670 val = ioread32(ar_pci->mem + offset); in ath10k_bus_pci_read32()
673 return val; in ath10k_bus_pci_read32()
695 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val) in ath10k_pci_soc_write32() argument
697 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val); in ath10k_pci_soc_write32()
705 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val) in ath10k_pci_reg_write32() argument
854 u32 val = 0, region = addr & 0xfffff; ath10k_pci_qca988x_targ_cpu_to_ce_addr() local
869 u32 val = 0, region = addr & 0xfffff; ath10k_pci_qca6174_targ_cpu_to_ce_addr() local
879 u32 val = 0, region = addr & 0xfffff; ath10k_pci_qca99x0_targ_cpu_to_ce_addr() local
1010 __le32 val = 0; ath10k_pci_diag_read32() local
1165 __le32 val = __cpu_to_le32(value); ath10k_pci_diag_write32() local
1565 u32 val; ath10k_pci_set_ram_config() local
1880 u32 val; ath10k_pci_irq_msi_fw_mask() local
1908 u32 val; ath10k_pci_irq_msi_fw_unmask() local
2269 u32 addr, val; ath10k_pci_wake_target_cpu() local
2553 u32 val; ath10k_pci_fw_crashed_clear() local
2562 u32 val; ath10k_pci_has_device_gone() local
2571 u32 val; ath10k_pci_warm_reset_si0() local
2590 u32 val; ath10k_pci_warm_reset_cpu() local
2601 u32 val; ath10k_pci_warm_reset_ce() local
2614 u32 val; ath10k_pci_warm_reset_clear_lf() local
2678 u32 val; ath10k_pci_qca988x_chip_reset() local
2914 u32 val; ath10k_pci_resume() local
3286 u32 val; ath10k_pci_wait_for_target_init() local
3341 u32 val; ath10k_pci_cold_reset() local
[all...]
/kernel/linux/linux-5.10/drivers/net/dsa/
H A Dlantiq_gswip.c283 u16 val[5]; member
347 static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset) in gswip_switch_w() argument
349 __raw_writel(val, priv->gswip + (offset * 4)); in gswip_switch_w()
355 u32 val = gswip_switch_r(priv, offset); in gswip_switch_mask() local
357 val &= ~(clear); in gswip_switch_mask()
358 val |= set; in gswip_switch_mask()
359 gswip_switch_w(priv, val, offset); in gswip_switch_mask()
365 u32 val; in gswip_switch_r_timeout() local
367 return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val, in gswip_switch_r_timeout()
368 (val in gswip_switch_r_timeout()
376 gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset) gswip_mdio_w() argument
384 u32 val = gswip_mdio_r(priv, offset); gswip_mdio_mask() local
396 gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset) gswip_mii_w() argument
404 u32 val = gswip_mii_r(priv, offset); gswip_mii_mask() local
450 gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val) gswip_mdio_wr() argument
[all...]
/kernel/linux/linux-6.6/arch/powerpc/kvm/
H A Dmpic.c125 u32 val, int idx);
129 uint32_t val);
580 uint32_t val) in write_IRQreg_idr()
594 src->idr = val & mask; in write_IRQreg_idr()
625 uint32_t val) in write_IRQreg_ilr()
630 src->output = val & ILR_INTTGT_MASK; in write_IRQreg_ilr()
639 uint32_t val) in write_IRQreg_ivpr()
651 (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask); in write_IRQreg_ivpr()
673 pr_debug("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ, val, in write_IRQreg_ivpr()
677 static void openpic_gcr_write(struct openpic *opp, uint64_t val) in openpic_gcr_write() argument
579 write_IRQreg_idr(struct openpic *opp, int n_IRQ, uint32_t val) write_IRQreg_idr() argument
624 write_IRQreg_ilr(struct openpic *opp, int n_IRQ, uint32_t val) write_IRQreg_ilr() argument
638 write_IRQreg_ivpr(struct openpic *opp, int n_IRQ, uint32_t val) write_IRQreg_ivpr() argument
688 openpic_gbl_write(void *opaque, gpa_t addr, u32 val) openpic_gbl_write() argument
806 openpic_tmr_write(void *opaque, gpa_t addr, u32 val) openpic_tmr_write() argument
886 openpic_src_write(void *opaque, gpa_t addr, u32 val) openpic_src_write() argument
940 openpic_msi_write(void *opaque, gpa_t addr, u32 val) openpic_msi_write() argument
1015 openpic_summary_write(void *opaque, gpa_t addr, u32 val) openpic_summary_write() argument
1023 openpic_cpu_write_internal(void *opaque, gpa_t addr, u32 val, int idx) openpic_cpu_write_internal() argument
1118 openpic_cpu_write(void *opaque, gpa_t addr, u32 val) openpic_cpu_write() argument
1355 kvm_mpic_write_internal(struct openpic *opp, gpa_t addr, u32 val) kvm_mpic_write_internal() argument
1378 u32 val; kvm_mpic_read() member
1496 access_reg(struct openpic *opp, gpa_t addr, u32 *val, int type) access_reg() argument
[all...]
/kernel/linux/linux-5.10/sound/pci/
H A Drme96.c499 snd_rme96_write_SPI(struct rme96 *rme96, u16 val) in snd_rme96_write_SPI() argument
504 if (val & 0x8000) { in snd_rme96_write_SPI()
515 val <<= 1; in snd_rme96_write_SPI()
1877 unsigned int val; in snd_rme96_put_loopback_control() local
1880 val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL; in snd_rme96_put_loopback_control()
1882 val = (rme96->wcreg & ~RME96_WCR_SEL) | val; in snd_rme96_put_loopback_control()
1883 change = val != rme96->wcreg; in snd_rme96_put_loopback_control()
1884 rme96->wcreg = val; in snd_rme96_put_loopback_control()
1885 writel(val, rme9 in snd_rme96_put_loopback_control()
1969 unsigned int val; snd_rme96_put_inputtype_control() local
2028 unsigned int val; snd_rme96_put_clockmode_control() local
2062 unsigned int val; snd_rme96_put_attenuation_control() local
2095 unsigned int val; snd_rme96_put_montracks_control() local
2108 u32 val = 0; snd_rme96_convert_from_aes() local
2118 snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val) snd_rme96_convert_to_aes() argument
2147 u32 val; snd_rme96_control_spdif_put() local
2176 u32 val; snd_rme96_control_spdif_stream_put() local
2445 u8 val; snd_rme96_probe() local
[all...]
/kernel/linux/linux-5.10/drivers/spi/
H A Dspi-tegra114.c70 #define SPI_CS_SETUP_HOLD(reg, cs, val) \
71 ((((val) & 0xFFu) << ((cs) * 8)) | \
83 #define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val) \
84 (reg = (((val) & 0x1) << ((cs) * 8 + 5)) | \
86 #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val) \
87 (reg = (((val) & 0x1F) << ((cs) * 8)) | \
93 #define SPI_BLK_CNT(val) (((val) >> 0) & 0xFFFF)
94 #define SPI_SLV_IDLE_COUNT(val) (((val) >> 1
233 tegra_spi_writel(struct tegra_spi_data *tspi, u32 val, unsigned long reg) tegra_spi_writel() argument
245 u32 val; tegra_spi_clear_status() local
538 u32 val; tegra_spi_start_dma_based_transfer() local
632 u32 val; tegra_spi_start_cpu_based_transfer() local
952 u32 val; tegra_spi_setup() local
[all...]
/kernel/linux/linux-6.6/drivers/net/dsa/
H A Dlantiq_gswip.c296 u16 val[5]; member
360 static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset) in gswip_switch_w() argument
362 __raw_writel(val, priv->gswip + (offset * 4)); in gswip_switch_w()
368 u32 val = gswip_switch_r(priv, offset); in gswip_switch_mask() local
370 val &= ~(clear); in gswip_switch_mask()
371 val |= set; in gswip_switch_mask()
372 gswip_switch_w(priv, val, offset); in gswip_switch_mask()
378 u32 val; in gswip_switch_r_timeout() local
380 return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val, in gswip_switch_r_timeout()
381 (val in gswip_switch_r_timeout()
389 gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset) gswip_mdio_w() argument
397 u32 val = gswip_mdio_r(priv, offset); gswip_mdio_mask() local
409 gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset) gswip_mii_w() argument
417 u32 val = gswip_mii_r(priv, offset); gswip_mii_mask() local
463 gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val) gswip_mdio_wr() argument
[all...]
/kernel/linux/linux-6.6/drivers/spi/
H A Dspi-imx.c154 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
157 *(type *)spi_imx->rx_buf = val; \
167 type val = 0; \
170 val = *(type *)spi_imx->tx_buf; \
176 writel(val, spi_imx->base + MXC_CSPITXDATA); \
309 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); in spi_imx_buf_rx_swap_u32() local
317 swab32s(&val); in spi_imx_buf_rx_swap_u32()
319 swahw32s(&val); in spi_imx_buf_rx_swap_u32()
321 *(u32 *)spi_imx->rx_buf = val; in spi_imx_buf_rx_swap_u32()
331 u32 val; in spi_imx_buf_rx_swap() local
358 u32 val = 0; spi_imx_buf_tx_swap_u32() local
383 u32 val = 0; spi_imx_buf_tx_swap() local
410 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA)); mx53_ecspi_rx_target() local
430 u32 val = 0; mx53_ecspi_tx_target() local
488 unsigned int val = 0; mx51_ecspi_intctrl() local
761 unsigned int val = 0; mx31_intctrl() local
865 unsigned int val = 0; mx21_intctrl() local
940 unsigned int val = 0; mx1_intctrl() local
1724 u32 val; spi_imx_probe() local
[all...]
H A Dspi-tegra114.c69 #define SPI_CS_SETUP_HOLD(reg, cs, val) \
70 ((((val) & 0xFFu) << ((cs) * 8)) | \
82 #define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val) \
83 (reg = (((val) & 0x1) << ((cs) * 8 + 5)) | \
85 #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val) \
86 (reg = (((val) & 0x1F) << ((cs) * 8)) | \
92 #define SPI_BLK_CNT(val) (((val) >> 0) & 0xFFFF)
93 #define SPI_SLV_IDLE_COUNT(val) (((val) >> 1
232 tegra_spi_writel(struct tegra_spi_data *tspi, u32 val, unsigned long reg) tegra_spi_writel() argument
244 u32 val; tegra_spi_clear_status() local
537 u32 val; tegra_spi_start_dma_based_transfer() local
631 u32 val; tegra_spi_start_cpu_based_transfer() local
947 u32 val; tegra_spi_setup() local
[all...]
H A Dspi-bcm-qspi.c519 u32 val, mask; in bcm_qspi_bspi_set_mode() local
521 val = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL); in bcm_qspi_bspi_set_mode()
523 if (val & mask || qspi->s3_strap_override_ctrl & mask) { in bcm_qspi_bspi_set_mode()
801 u32 val; in read_rxram_slot_u32() local
803 val = bcm_qspi_read(qspi, MSPI, offset); in read_rxram_slot_u32()
804 val = swap4bytes(val); in read_rxram_slot_u32()
806 return val; in read_rxram_slot_u32()
884 u8 val) in write_txram_slot_u8()
889 bcm_qspi_write(qspi, MSPI, reg_offset, val); in write_txram_slot_u8()
883 write_txram_slot_u8(struct bcm_qspi *qspi, int slot, u8 val) write_txram_slot_u8() argument
892 write_txram_slot_u16(struct bcm_qspi *qspi, int slot, u16 val) write_txram_slot_u16() argument
903 write_txram_slot_u32(struct bcm_qspi *qspi, int slot, u32 val) write_txram_slot_u32() argument
912 write_txram_slot_u64(struct bcm_qspi *qspi, int slot, u64 val) write_txram_slot_u64() argument
930 write_cdram_slot(struct bcm_qspi *qspi, int slot, u32 val) write_cdram_slot() argument
951 u8 val = buf ? buf[tp.byte] : 0x00; write_to_hw() local
957 u16 val = buf ? buf[tp.byte / 2] : 0x0000; write_to_hw() local
963 u32 val = buf ? buf[tp.byte/4] : 0x0; write_to_hw() local
969 u64 val = (buf ? buf[tp.byte/8] : 0x0); write_to_hw() local
1389 u32 val = 0; bcm_qspi_bspi_init() local
1492 u32 val; bcm_qspi_probe() local
[all...]
/kernel/linux/linux-6.6/sound/pci/
H A Drme96.c472 snd_rme96_write_SPI(struct rme96 *rme96, u16 val) in snd_rme96_write_SPI() argument
477 if (val & 0x8000) { in snd_rme96_write_SPI()
488 val <<= 1; in snd_rme96_write_SPI()
1842 unsigned int val; in snd_rme96_put_loopback_control() local
1845 val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL; in snd_rme96_put_loopback_control()
1847 val = (rme96->wcreg & ~RME96_WCR_SEL) | val; in snd_rme96_put_loopback_control()
1848 change = val != rme96->wcreg; in snd_rme96_put_loopback_control()
1849 rme96->wcreg = val; in snd_rme96_put_loopback_control()
1850 writel(val, rme9 in snd_rme96_put_loopback_control()
1934 unsigned int val; snd_rme96_put_inputtype_control() local
1993 unsigned int val; snd_rme96_put_clockmode_control() local
2027 unsigned int val; snd_rme96_put_attenuation_control() local
2060 unsigned int val; snd_rme96_put_montracks_control() local
2073 u32 val = 0; snd_rme96_convert_from_aes() local
2083 snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val) snd_rme96_convert_to_aes() argument
2112 u32 val; snd_rme96_control_spdif_put() local
2141 u32 val; snd_rme96_control_spdif_stream_put() local
2414 u8 val; __snd_rme96_probe() local
[all...]

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