Lines Matching refs:val
70 #define SPI_CS_SETUP_HOLD(reg, cs, val) \
71 ((((val) & 0xFFu) << ((cs) * 8)) | \
83 #define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val) \
84 (reg = (((val) & 0x1) << ((cs) * 8 + 5)) | \
86 #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val) \
87 (reg = (((val) & 0x1F) << ((cs) * 8)) | \
93 #define SPI_BLK_CNT(val) (((val) >> 0) & 0xFFFF)
94 #define SPI_SLV_IDLE_COUNT(val) (((val) >> 16) & 0xFF)
109 #define SPI_TX_FIFO_EMPTY_COUNT(val) (((val) >> 16) & 0x7F)
110 #define SPI_RX_FIFO_FULL_COUNT(val) (((val) >> 23) & 0x7F)
234 u32 val, unsigned long reg)
236 writel(val, tspi->base + reg);
245 u32 val;
248 val = tegra_spi_readl(tspi, SPI_TRANS_STATUS);
249 tegra_spi_writel(tspi, val, SPI_TRANS_STATUS);
252 val = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
253 if (val & SPI_ERR)
538 u32 val;
544 val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1);
545 tegra_spi_writel(tspi, val, SPI_DMA_BLK);
555 val |= SPI_TX_TRIG_1 | SPI_RX_TRIG_1;
558 val |= SPI_TX_TRIG_4 | SPI_RX_TRIG_4;
561 val |= SPI_TX_TRIG_8 | SPI_RX_TRIG_8;
567 val |= SPI_IE_TX;
570 val |= SPI_IE_RX;
573 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
574 tspi->dma_control_reg = val;
622 tspi->dma_control_reg = val;
624 val |= SPI_DMA_EN;
625 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
632 u32 val;
640 val = SPI_DMA_BLK_SET(cur_words - 1);
641 tegra_spi_writel(tspi, val, SPI_DMA_BLK);
643 val = 0;
645 val |= SPI_IE_TX;
648 val |= SPI_IE_RX;
650 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
651 tspi->dma_control_reg = val;
655 val = tspi->command1_reg;
656 val |= SPI_PIO;
657 tegra_spi_writel(tspi, val, SPI_COMMAND1);
952 u32 val;
977 val = tegra_spi_readl(tspi, SPI_INTR_MASK);
978 val &= ~SPI_INTR_ALL_MASK;
979 tegra_spi_writel(tspi, val, SPI_INTR_MASK);
987 val = tspi->def_command1_reg;
989 val &= ~SPI_CS_POL_INACTIVE(spi->chip_select);
991 val |= SPI_CS_POL_INACTIVE(spi->chip_select);
992 tspi->def_command1_reg = val;