Lines Matching refs:val
69 #define SPI_CS_SETUP_HOLD(reg, cs, val) \
70 ((((val) & 0xFFu) << ((cs) * 8)) | \
82 #define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val) \
83 (reg = (((val) & 0x1) << ((cs) * 8 + 5)) | \
85 #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val) \
86 (reg = (((val) & 0x1F) << ((cs) * 8)) | \
92 #define SPI_BLK_CNT(val) (((val) >> 0) & 0xFFFF)
93 #define SPI_SLV_IDLE_COUNT(val) (((val) >> 16) & 0xFF)
108 #define SPI_TX_FIFO_EMPTY_COUNT(val) (((val) >> 16) & 0x7F)
109 #define SPI_RX_FIFO_FULL_COUNT(val) (((val) >> 23) & 0x7F)
233 u32 val, unsigned long reg)
235 writel(val, tspi->base + reg);
244 u32 val;
247 val = tegra_spi_readl(tspi, SPI_TRANS_STATUS);
248 tegra_spi_writel(tspi, val, SPI_TRANS_STATUS);
251 val = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
252 if (val & SPI_ERR)
537 u32 val;
543 val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1);
544 tegra_spi_writel(tspi, val, SPI_DMA_BLK);
554 val |= SPI_TX_TRIG_1 | SPI_RX_TRIG_1;
557 val |= SPI_TX_TRIG_4 | SPI_RX_TRIG_4;
560 val |= SPI_TX_TRIG_8 | SPI_RX_TRIG_8;
566 val |= SPI_IE_TX;
569 val |= SPI_IE_RX;
572 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
573 tspi->dma_control_reg = val;
621 tspi->dma_control_reg = val;
623 val |= SPI_DMA_EN;
624 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
631 u32 val;
639 val = SPI_DMA_BLK_SET(cur_words - 1);
640 tegra_spi_writel(tspi, val, SPI_DMA_BLK);
642 val = 0;
644 val |= SPI_IE_TX;
647 val |= SPI_IE_RX;
649 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
650 tspi->dma_control_reg = val;
654 val = tspi->command1_reg;
655 val |= SPI_PIO;
656 tegra_spi_writel(tspi, val, SPI_COMMAND1);
947 u32 val;
971 val = tegra_spi_readl(tspi, SPI_INTR_MASK);
972 val &= ~SPI_INTR_ALL_MASK;
973 tegra_spi_writel(tspi, val, SPI_INTR_MASK);
981 val = tspi->def_command1_reg;
983 val &= ~SPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0));
985 val |= SPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0));
986 tspi->def_command1_reg = val;