Lines Matching refs:val
269 u32 val;
271 val = readl_relaxed(drv->base + offset);
272 val &= ~mask;
273 val |= value & mask;
274 writel_relaxed(val, drv->base + offset);
306 u32 val, mask;
310 val = desc->timer_cons_down << RBIF_TIMER_ADJ_CONS_DOWN_SHIFT;
311 val |= desc->timer_cons_up << RBIF_TIMER_ADJ_CONS_UP_SHIFT;
313 cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST, mask, val);
321 val = RBCPR_CTL_LOOP_EN;
323 val = 0;
324 cpr_ctl_modify(drv, RBCPR_CTL_LOOP_EN, val);
462 u32 val, error_steps, reg_mask;
476 val = cpr_read(drv, REG_RBCPR_RESULT_0);
478 error_steps = val >> RBCPR_RESULT0_ERROR_STEPS_SHIFT;
500 val = reg_mask;
501 cpr_ctl_modify(drv, reg_mask, val);
536 val = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
538 cpr_ctl_modify(drv, reg_mask, val);
568 val = 0;
573 val = desc->up_threshold;
574 val <<= RBCPR_CTL_UP_THRESHOLD_SHIFT;
577 cpr_ctl_modify(drv, reg_mask, val);
593 u32 val;
597 val = cpr_read(drv, REG_RBIF_IRQ_STATUS);
599 val = cpr_read(drv, REG_RBIF_IRQ_STATUS);
601 dev_dbg(drv->dev, "IRQ_STATUS = %#02x\n", val);
609 val = cpr_read(drv, REG_RBCPR_CTL);
612 val);
619 if (val & CPR_INT_UP) {
621 } else if (val & CPR_INT_DOWN) {
623 } else if (val & CPR_INT_MIN) {
625 } else if (val & CPR_INT_MAX) {
627 } else if (val & CPR_INT_MID) {
632 "IRQ occurred for unknown flag (%#08x)\n", val);
682 u32 val, gcnt;
691 val = (RBIF_LIMIT_CEILING_DEFAULT & RBIF_LIMIT_CEILING_MASK)
693 val |= RBIF_LIMIT_FLOOR_DEFAULT & RBIF_LIMIT_FLOOR_MASK;
694 cpr_write(drv, REG_RBIF_LIMIT, val);
711 val = (drv->ref_clk_khz * desc->timer_delay_us) / 1000;
712 cpr_write(drv, REG_RBCPR_TIMER_INTERVAL, val);
713 dev_dbg(drv->dev, "Timer count: %#0x (for %d us)\n", val,
717 val = desc->timer_cons_down << RBIF_TIMER_ADJ_CONS_DOWN_SHIFT;
718 val |= desc->timer_cons_up << RBIF_TIMER_ADJ_CONS_UP_SHIFT;
719 val |= desc->clamp_timer_interval << RBIF_TIMER_ADJ_CLAMP_INT_SHIFT;
720 cpr_write(drv, REG_RBIF_TIMER_ADJUST, val);
723 val = desc->up_threshold << RBCPR_CTL_UP_THRESHOLD_SHIFT;
724 val |= desc->down_threshold << RBCPR_CTL_DN_THRESHOLD_SHIFT;
725 val |= RBCPR_CTL_TIMER_EN | RBCPR_CTL_COUNT_MODE;
726 val |= RBCPR_CTL_SW_AUTO_CONT_ACK_EN;
727 cpr_write(drv, REG_RBCPR_CTL, val);
731 corner->save_ctl = val;
737 val = cpr_read(drv, REG_RBCPR_VERSION);
738 if (val <= RBCPR_VER_2)