Lines Matching refs:val
270 u32 val;
272 val = readl_relaxed(drv->base + offset);
273 val &= ~mask;
274 val |= value & mask;
275 writel_relaxed(val, drv->base + offset);
307 u32 val, mask;
311 val = desc->timer_cons_down << RBIF_TIMER_ADJ_CONS_DOWN_SHIFT;
312 val |= desc->timer_cons_up << RBIF_TIMER_ADJ_CONS_UP_SHIFT;
314 cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST, mask, val);
322 val = RBCPR_CTL_LOOP_EN;
324 val = 0;
325 cpr_ctl_modify(drv, RBCPR_CTL_LOOP_EN, val);
463 u32 val, error_steps, reg_mask;
477 val = cpr_read(drv, REG_RBCPR_RESULT_0);
479 error_steps = val >> RBCPR_RESULT0_ERROR_STEPS_SHIFT;
501 val = reg_mask;
502 cpr_ctl_modify(drv, reg_mask, val);
537 val = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
539 cpr_ctl_modify(drv, reg_mask, val);
569 val = 0;
574 val = desc->up_threshold;
575 val <<= RBCPR_CTL_UP_THRESHOLD_SHIFT;
578 cpr_ctl_modify(drv, reg_mask, val);
594 u32 val;
598 val = cpr_read(drv, REG_RBIF_IRQ_STATUS);
600 val = cpr_read(drv, REG_RBIF_IRQ_STATUS);
602 dev_dbg(drv->dev, "IRQ_STATUS = %#02x\n", val);
610 val = cpr_read(drv, REG_RBCPR_CTL);
613 val);
620 if (val & CPR_INT_UP) {
622 } else if (val & CPR_INT_DOWN) {
624 } else if (val & CPR_INT_MIN) {
626 } else if (val & CPR_INT_MAX) {
628 } else if (val & CPR_INT_MID) {
633 "IRQ occurred for unknown flag (%#08x)\n", val);
683 u32 val, gcnt;
692 val = (RBIF_LIMIT_CEILING_DEFAULT & RBIF_LIMIT_CEILING_MASK)
694 val |= RBIF_LIMIT_FLOOR_DEFAULT & RBIF_LIMIT_FLOOR_MASK;
695 cpr_write(drv, REG_RBIF_LIMIT, val);
712 val = (drv->ref_clk_khz * desc->timer_delay_us) / 1000;
713 cpr_write(drv, REG_RBCPR_TIMER_INTERVAL, val);
714 dev_dbg(drv->dev, "Timer count: %#0x (for %d us)\n", val,
718 val = desc->timer_cons_down << RBIF_TIMER_ADJ_CONS_DOWN_SHIFT;
719 val |= desc->timer_cons_up << RBIF_TIMER_ADJ_CONS_UP_SHIFT;
720 val |= desc->clamp_timer_interval << RBIF_TIMER_ADJ_CLAMP_INT_SHIFT;
721 cpr_write(drv, REG_RBIF_TIMER_ADJUST, val);
724 val = desc->up_threshold << RBCPR_CTL_UP_THRESHOLD_SHIFT;
725 val |= desc->down_threshold << RBCPR_CTL_DN_THRESHOLD_SHIFT;
726 val |= RBCPR_CTL_TIMER_EN | RBCPR_CTL_COUNT_MODE;
727 val |= RBCPR_CTL_SW_AUTO_CONT_ACK_EN;
728 cpr_write(drv, REG_RBCPR_CTL, val);
732 corner->save_ctl = val;
738 val = cpr_read(drv, REG_RBCPR_VERSION);
739 if (val <= RBCPR_VER_2)