Lines Matching refs:val
432 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
435 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON;
654 u32 val;
657 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) {
659 offset, offset + sizeof(val), ar_pci->mem_len);
670 val = ioread32(ar_pci->mem + offset);
673 return val;
695 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val)
697 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);
705 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
707 ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val);
854 u32 val = 0, region = addr & 0xfffff;
856 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS)
858 val |= 0x100000 | region;
859 return val;
869 u32 val = 0, region = addr & 0xfffff;
871 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS)
873 val |= ((addr >= 0x100000) ? 0x100000 : 0) | region;
874 return val;
879 u32 val = 0, region = addr & 0xfffff;
881 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);
882 val |= 0x100000 | region;
883 return val;
1010 __le32 val = 0;
1013 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val));
1014 *value = __le32_to_cpu(val);
1165 __le32 val = __cpu_to_le32(value);
1167 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val));
1565 u32 val;
1570 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1572 if (val != config) {
1574 val, config);
1880 u32 val;
1887 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1889 val &= ~CORE_CTRL_PCIE_REG_31_MASK;
1891 CORE_CTRL_ADDRESS, val);
1908 u32 val;
1915 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1917 val |= CORE_CTRL_PCIE_REG_31_MASK;
1919 CORE_CTRL_ADDRESS, val);
2268 u32 addr, val;
2271 val = ath10k_pci_read32(ar, addr);
2272 val |= CORE_CTRL_CPU_INTR_MASK;
2273 ath10k_pci_write32(ar, addr, val);
2426 ath10k_err(ar, "Failed to get early alloc val: %d\n", ret);
2439 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret);
2448 ath10k_err(ar, "Failed to get option val: %d\n", ret);
2456 ath10k_err(ar, "Failed to set option val: %d\n", ret);
2552 u32 val;
2554 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2555 val &= ~FW_IND_EVENT_PENDING;
2556 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val);
2561 u32 val;
2563 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2564 return (val == 0xffffffff);
2570 u32 val;
2572 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2574 val | SOC_RESET_CONTROL_SI0_RST_MASK);
2575 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2579 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2581 val & ~SOC_RESET_CONTROL_SI0_RST_MASK);
2582 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2589 u32 val;
2593 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2595 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
2600 u32 val;
2602 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2605 val | SOC_RESET_CONTROL_CE_RST_MASK);
2608 val & ~SOC_RESET_CONTROL_CE_RST_MASK);
2613 u32 val;
2615 val = ath10k_pci_soc_read32(ar, SOC_LF_TIMER_CONTROL0_ADDRESS);
2617 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
2677 u32 val;
2714 &val);
2913 u32 val;
2927 pci_read_config_dword(pdev, 0x40, &val);
2928 if ((val & 0x0000ff00) != 0)
2929 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
3286 u32 val;
3293 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
3296 val);
3299 if (val == 0xffffffff)
3303 if (val & FW_IND_EVENT_PENDING)
3306 if (val & FW_IND_INITIALIZED)
3319 if (val == 0xffffffff) {
3324 if (val & FW_IND_EVENT_PENDING) {
3329 if (!(val & FW_IND_INITIALIZED)) {
3331 val);
3341 u32 val;
3352 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
3353 val |= 1;
3354 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
3364 val &= ~1;
3365 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);