Lines Matching refs:val
85 u32 val;
88 ret = regmap_read(drvdata->regmap, reg, &val);
95 return (u8)val;
105 u8 reg, u8 val)
107 return regmap_write(drvdata->regmap, reg, val);
117 u8 reg, u8 mask, u8 val)
119 return regmap_update_bits(drvdata->regmap, reg, mask, val);
390 u8 val;
392 val = si5351_reg_read(hwdata->drvdata, SI5351_PLL_INPUT_SOURCE);
394 return (val & mask) ? 1 : 0;
584 u8 val;
586 val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num);
588 return (val & SI5351_CLK_PLL_SELECT) ? 1 : 0;
807 u8 val;
814 val = SI5351_CLK_INPUT_MULTISYNTH_N;
819 val = SI5351_CLK_INPUT_MULTISYNTH_N;
821 val = SI5351_CLK_INPUT_MULTISYNTH_0_4;
824 val = SI5351_CLK_INPUT_XTAL;
830 val = SI5351_CLK_INPUT_CLKIN;
837 SI5351_CLK_INPUT_MASK, val);
880 u8 val;
887 val = SI5351_CLK_DISABLE_STATE_LOW;
890 val = SI5351_CLK_DISABLE_STATE_HIGH;
893 val = SI5351_CLK_DISABLE_STATE_FLOAT;
896 val = SI5351_CLK_DISABLE_STATE_NEVER;
902 si5351_set_bits(drvdata, reg, mask, val << shift);
909 u8 val = si5351_reg_read(drvdata, SI5351_CLK0_CTRL + num);
910 u8 mask = val & SI5351_CLK_PLL_SELECT ? SI5351_PLL_RESET_B :
915 switch (val & SI5351_CLK_INPUT_MASK) {
930 (val & SI5351_CLK_PLL_SELECT) ? 1 : 0);
971 unsigned char val;
973 val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num);
974 switch (val & SI5351_CLK_INPUT_MASK) {
1178 u32 val;
1198 p = of_prop_next_u32(prop, p, &val);
1205 switch (val) {
1213 val, num);
1220 "invalid parent %d for pll %d\n", val, num);
1240 &val)) {
1241 switch (val) {
1253 val, num);
1258 if (!of_property_read_u32(child, "silabs,clock-source", &val)) {
1259 switch (val) {
1276 val, num);
1285 val, num);
1291 &val)) {
1292 switch (val) {
1297 pdata->clkout[num].drive = val;
1302 val, num);
1308 &val)) {
1309 switch (val) {
1329 val, num);
1334 if (!of_property_read_u32(child, "clock-frequency", &val))
1335 pdata->clkout[num].rate = val;