| /kernel/linux/linux-5.10/drivers/clk/rockchip/ |
| H A D | clk-rk3036.c | 128 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; variable
148 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| H A D | clk-rk3128.c | 150 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; variable
185 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| H A D | clk-rk3228.c | 159 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; variable
199 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| H A D | clk-rk3288.c | 207 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; variable
262 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| H A D | clk-rk3368.c | 121 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; variable
257 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| H A D | clk-rk3328.c | 185 PNAME(mux_uart0_p) = { "clk_uart0_div", variable
252 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| H A D | clk-rv1108.c | 131 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; variable
167 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| H A D | clk-rk3308.c | 131 PNAME(mux_uart0_p) = { "clk_uart0_src", "dummy", "clk_uart0_frac" }; variable
198 MUX(0, "clk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
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| H A D | clk-rk3399.c | 204 PNAME(mux_uart0_p) = { "clk_uart0_div", "clk_uart0_frac", "xin24m" }; variable
262 MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| /kernel/linux/linux-6.6/drivers/clk/rockchip/ |
| H A D | clk-rk3036.c | 130 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; variable
150 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| H A D | clk-rk3228.c | 160 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; variable
200 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| H A D | clk-rk3128.c | 151 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; variable
186 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| H A D | clk-rv1108.c | 132 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; variable
168 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| H A D | clk-rk3288.c | 208 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; variable
263 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| H A D | clk-rk3368.c | 121 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; variable
259 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| H A D | clk-rk3328.c | 186 PNAME(mux_uart0_p) = { "clk_uart0_div", variable
253 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| H A D | clk-rv1126.c | 162 PNAME(mux_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" }; variable
224 MUX(SCLK_UART0_MUX, "sclk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
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| H A D | clk-rk3308.c | 132 PNAME(mux_uart0_p) = { "clk_uart0_src", "dummy", "clk_uart0_frac" }; variable
199 MUX(0, "clk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
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| H A D | clk-rk3399.c | 204 PNAME(mux_uart0_p) = { "clk_uart0_div", "clk_uart0_frac", "xin24m" }; variable
262 MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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