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Searched refs:div_core_shift (Results 1 - 25 of 29) sorted by relevance

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/kernel/linux/linux-5.10/drivers/clk/rockchip/
H A Dclk-cpu.c93 clksel0 >>= reg_data->div_core_shift; in rockchip_cpuclk_recalc_rate()
166 reg_data->div_core_shift) | in rockchip_cpuclk_pre_rate_change()
210 reg_data->div_core_shift) | in rockchip_cpuclk_post_rate_change()
H A Dclk-rk3188.c149 .div_core_shift = 0,
188 .div_core_shift = 9,
H A Dclk-rk3368.c158 .div_core_shift = 0,
168 .div_core_shift = 0,
H A Dclk-rk3036.c106 .div_core_shift = 0,
H A Dclk-rk3128.c121 .div_core_shift = 0,
H A Dclk-rk3228.c123 .div_core_shift = 0,
H A Dclk.h334 * @div_core_shift: core divider offset used to divide the pll value
343 u8 div_core_shift; member
H A Dclk-rk3288.c183 .div_core_shift = 8,
H A Dclk-rk3328.c134 .div_core_shift = 0,
H A Dclk-rv1108.c110 .div_core_shift = 0,
H A Dclk-rk3399.c295 .div_core_shift = 0,
305 .div_core_shift = 0,
H A Dclk-px30.c128 .div_core_shift = 0,
H A Dclk-rk3308.c113 .div_core_shift = 0,
/kernel/linux/linux-6.6/drivers/clk/rockchip/
H A Dclk-cpu.c89 clksel0 >>= reg_data->div_core_shift[0]; in rockchip_cpuclk_recalc_rate()
200 reg_data->div_core_shift[i]), in rockchip_cpuclk_pre_rate_change()
266 reg_data->div_core_shift[i]), in rockchip_cpuclk_post_rate_change()
H A Dclk-rk3588.c314 .div_core_shift[0] = 8,
317 .div_core_shift[1] = 0,
371 .div_core_shift[0] = 8,
374 .div_core_shift[1] = 0,
425 .div_core_shift[0] = 0,
428 .div_core_shift[1] = 7,
431 .div_core_shift[2] = 0,
434 .div_core_shift[3] = 7,
H A Dclk-rk3368.c158 .div_core_shift[0] = 0,
169 .div_core_shift[0] = 0,
H A Dclk-rk3188.c149 .div_core_shift[0] = 0,
189 .div_core_shift[0] = 9,
H A Dclk-rk3568.c195 .div_core_shift[0] = 0,
198 .div_core_shift[1] = 8,
201 .div_core_shift[2] = 0,
204 .div_core_shift[3] = 8,
H A Dclk-rk3036.c106 .div_core_shift[0] = 0,
H A Dclk-rk3228.c123 .div_core_shift[0] = 0,
H A Dclk-rk3128.c121 .div_core_shift[0] = 0,
H A Dclk-rv1108.c110 .div_core_shift[0] = 0,
H A Dclk-rk3288.c183 .div_core_shift[0] = 8,
H A Dclk-rk3328.c134 .div_core_shift[0] = 0,
H A Dclk-rk3399.c295 .div_core_shift[0] = 0,
306 .div_core_shift[0] = 0,

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