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/third_party/mesa3d/src/freedreno/vulkan/
H A Dtu_cs.c14 tu_cs_init(struct tu_cs *cs, in tu_cs_init() argument
21 memset(cs, 0, sizeof(*cs)); in tu_cs_init()
23 cs->device = device; in tu_cs_init()
24 cs->mode = mode; in tu_cs_init()
25 cs->next_bo_size = initial_size; in tu_cs_init()
32 tu_cs_init_external(struct tu_cs *cs, struct tu_device *device, in tu_cs_init_external() argument
35 memset(cs, 0, sizeof(*cs)); in tu_cs_init_external()
37 cs in tu_cs_init_external()
48 tu_cs_init_suballoc(struct tu_cs *cs, struct tu_device *device, struct tu_suballoc_bo *suballoc_bo) tu_cs_init_suballoc() argument
66 tu_cs_finish(struct tu_cs *cs) tu_cs_finish() argument
80 tu_cs_current_bo(const struct tu_cs *cs) tu_cs_current_bo() argument
95 tu_cs_get_offset(const struct tu_cs *cs) tu_cs_get_offset() argument
105 tu_cs_add_bo(struct tu_cs *cs, uint32_t size) tu_cs_add_bo() argument
154 tu_cs_reserve_entry(struct tu_cs *cs) tu_cs_reserve_entry() argument
179 tu_cs_add_entry(struct tu_cs *cs) tu_cs_add_entry() argument
208 tu_cs_add_entries(struct tu_cs *cs, struct tu_cs *target) tu_cs_add_entries() argument
233 tu_cs_begin(struct tu_cs *cs) tu_cs_begin() argument
244 tu_cs_end(struct tu_cs *cs) tu_cs_end() argument
261 tu_cs_begin_sub_stream(struct tu_cs *cs, uint32_t size, struct tu_cs *sub_cs) tu_cs_begin_sub_stream() argument
284 tu_cs_alloc(struct tu_cs *cs, uint32_t count, uint32_t size, struct tu_cs_memory *memory) tu_cs_alloc() argument
320 tu_cs_end_sub_stream(struct tu_cs *cs, struct tu_cs *sub_cs) tu_cs_end_sub_stream() argument
346 tu_cs_reserve_space(struct tu_cs *cs, uint32_t reserved_size) tu_cs_reserve_space() argument
415 tu_cs_reset(struct tu_cs *cs) tu_cs_reset() argument
[all...]
H A Dtu_cs.h111 tu_cs_init(struct tu_cs *cs,
117 tu_cs_init_external(struct tu_cs *cs, struct tu_device *device,
121 tu_cs_init_suballoc(struct tu_cs *cs, struct tu_device *device,
125 tu_cs_finish(struct tu_cs *cs);
128 tu_cs_begin(struct tu_cs *cs);
131 tu_cs_end(struct tu_cs *cs);
134 tu_cs_begin_sub_stream(struct tu_cs *cs, uint32_t size, struct tu_cs *sub_cs);
137 tu_cs_alloc(struct tu_cs *cs,
143 tu_cs_end_sub_stream(struct tu_cs *cs, struct tu_cs *sub_cs);
146 tu_cs_end_draw_state(struct tu_cs *cs, struc argument
159 tu_cs_draw_state(struct tu_cs *sub_cs, struct tu_cs *cs, uint32_t size) tu_cs_draw_state() argument
186 tu_cs_get_size(const struct tu_cs *cs) tu_cs_get_size() argument
196 tu_cs_is_empty(const struct tu_cs *cs) tu_cs_is_empty() argument
206 tu_cs_discard_entries(struct tu_cs *cs) tu_cs_discard_entries() argument
216 tu_cs_get_call_size(const struct tu_cs *cs) tu_cs_get_call_size() argument
227 tu_cs_sanity_check(const struct tu_cs *cs) tu_cs_sanity_check() argument
241 tu_cs_emit(struct tu_cs *cs, uint32_t value) tu_cs_emit() argument
258 tu_cs_emit_array(struct tu_cs *cs, const uint32_t *values, uint32_t length) tu_cs_emit_array() argument
269 tu_cs_get_space(const struct tu_cs *cs) tu_cs_get_space() argument
275 tu_cs_reserve(struct tu_cs *cs, uint32_t reserved_size) tu_cs_reserve() argument
298 tu_cs_emit_pkt4(struct tu_cs *cs, uint16_t regindx, uint16_t cnt) tu_cs_emit_pkt4() argument
308 tu_cs_emit_pkt7(struct tu_cs *cs, uint8_t opcode, uint16_t cnt) tu_cs_emit_pkt7() argument
319 tu_cs_emit_wfi(struct tu_cs *cs) tu_cs_emit_wfi() argument
325 tu_cs_emit_qw(struct tu_cs *cs, uint64_t value) tu_cs_emit_qw() argument
332 tu_cs_emit_write_reg(struct tu_cs *cs, uint16_t reg, uint32_t value) tu_cs_emit_write_reg() argument
342 tu_cs_emit_ib(struct tu_cs *cs, const struct tu_cs_entry *entry) tu_cs_emit_ib() argument
356 tu_cs_emit_state_ib(struct tu_cs *cs, struct tu_draw_state state) tu_cs_emit_state_ib() argument
370 tu_cs_emit_call(struct tu_cs *cs, const struct tu_cs *target) tu_cs_emit_call() argument
381 tu_cond_exec_start(struct tu_cs *cs, uint32_t cond_flags) tu_cond_exec_start() argument
403 tu_cond_exec_end(struct tu_cs *cs) tu_cond_exec_end() argument
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H A Dtu_query.c586 struct tu_cs *cs, in copy_query_value_gpu()
595 tu_cs_emit_pkt7(cs, CP_MEM_TO_MEM, 5); in copy_query_value_gpu()
598 tu_cs_emit(cs, mem_to_mem_flags); in copy_query_value_gpu()
599 tu_cs_emit_qw(cs, write_iova); in copy_query_value_gpu()
600 tu_cs_emit_qw(cs, src_iova); in copy_query_value_gpu()
605 struct tu_cs *cs, in emit_copy_query_pool_results()
623 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0); in emit_copy_query_pool_results()
635 tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6); in emit_copy_query_pool_results()
636 tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) | in emit_copy_query_pool_results()
638 tu_cs_emit_qw(cs, available_iov in emit_copy_query_pool_results()
585 copy_query_value_gpu(struct tu_cmd_buffer *cmdbuf, struct tu_cs *cs, uint64_t src_iova, uint64_t base_write_iova, uint32_t offset, VkQueryResultFlags flags) copy_query_value_gpu() argument
604 emit_copy_query_pool_results(struct tu_cmd_buffer *cmdbuf, struct tu_cs *cs, struct tu_query_pool *pool, uint32_t firstQuery, uint32_t queryCount, struct tu_buffer *buffer, VkDeviceSize dstOffset, VkDeviceSize stride, VkQueryResultFlags flags) emit_copy_query_pool_results() argument
707 struct tu_cs *cs = &cmdbuf->cs; tu_CmdCopyQueryPoolResults() local
731 struct tu_cs *cs = &cmdbuf->cs; emit_reset_query_pool() local
830 struct tu_cs *cs = cmdbuf->state.pass ? &cmdbuf->draw_cs : &cmdbuf->cs; emit_begin_occlusion_query() local
849 struct tu_cs *cs = cmdbuf->state.pass ? &cmdbuf->draw_cs : &cmdbuf->cs; emit_begin_stat_query() local
894 emit_perfcntrs_pass_start(struct tu_cs *cs, uint32_t pass) emit_perfcntrs_pass_start() argument
909 struct tu_cs *cs = cmdbuf->state.pass ? &cmdbuf->draw_cs : &cmdbuf->cs; emit_begin_perf_query() local
988 struct tu_cs *cs = cmdbuf->state.pass ? &cmdbuf->draw_cs : &cmdbuf->cs; emit_begin_xfb_query() local
1000 struct tu_cs *cs = cmdbuf->state.pass ? &cmdbuf->draw_cs : &cmdbuf->cs; emit_begin_prim_generated_query() local
1115 struct tu_cs *cs = pass ? &cmdbuf->draw_cs : &cmdbuf->cs; emit_end_occlusion_query() local
1179 emit_stop_primitive_ctrs(struct tu_cmd_buffer *cmdbuf, struct tu_cs *cs, enum VkQueryType query_type) emit_stop_primitive_ctrs() argument
1220 struct tu_cs *cs = cmdbuf->state.pass ? &cmdbuf->draw_cs : &cmdbuf->cs; emit_end_stat_query() local
1283 struct tu_cs *cs = cmdbuf->state.pass ? &cmdbuf->draw_cs : &cmdbuf->cs; emit_end_perf_query() local
1363 struct tu_cs *cs = cmdbuf->state.pass ? &cmdbuf->draw_cs : &cmdbuf->cs; emit_end_xfb_query() local
1411 struct tu_cs *cs = cmdbuf->state.pass ? &cmdbuf->draw_cs : &cmdbuf->cs; emit_end_prim_generated_query() local
1493 struct tu_cs *cs = &cmd->draw_epilogue_cs; handle_multiview_queries() local
1572 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs; tu_CmdWriteTimestamp2() local
[all...]
H A Dtu_clear_blit.c68 r2d_coords(struct tu_cs *cs, in r2d_coords() argument
73 tu_cs_emit_regs(cs, in r2d_coords()
80 tu_cs_emit_regs(cs, in r2d_coords()
88 r2d_clear_value(struct tu_cs *cs, enum pipe_format format, const VkClearValue *val) in r2d_clear_value() argument
143 tu_cs_emit_pkt4(cs, REG_A6XX_RB_2D_SRC_SOLID_C0, 4); in r2d_clear_value()
144 tu_cs_emit_array(cs, clear_value, 4); in r2d_clear_value()
182 struct tu_cs *cs, in r2d_src()
200 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PS_2D_SRC_INFO, 5); in r2d_src()
201 tu_cs_emit(cs, src_info); in r2d_src()
202 tu_cs_emit(cs, ivie in r2d_src()
181 r2d_src(struct tu_cmd_buffer *cmd, struct tu_cs *cs, const struct fdl6_view *iview, uint32_t layer, VkFilter filter, enum pipe_format dst_format) r2d_src() argument
210 r2d_src_depth(struct tu_cmd_buffer *cmd, struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer, VkFilter filter) r2d_src_depth() argument
228 r2d_src_stencil(struct tu_cmd_buffer *cmd, struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer, VkFilter filter) r2d_src_stencil() argument
243 r2d_src_buffer(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum pipe_format format, uint64_t va, uint32_t pitch, uint32_t width, uint32_t height, enum pipe_format dst_format) r2d_src_buffer() argument
267 r2d_dst(struct tu_cs *cs, const struct fdl6_view *iview, uint32_t layer, enum pipe_format src_format) r2d_dst() argument
286 r2d_dst_depth(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer) r2d_dst_depth() argument
298 r2d_dst_stencil(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer) r2d_dst_stencil() argument
307 r2d_dst_buffer(struct tu_cs *cs, enum pipe_format format, uint64_t va, uint32_t pitch, enum pipe_format src_format) r2d_dst_buffer() argument
325 r2d_setup_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum pipe_format src_format, enum pipe_format dst_format, VkImageAspectFlags aspect_mask, unsigned blit_param, bool clear, bool ubwc, bool scissor) r2d_setup_common() argument
387 r2d_setup(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum pipe_format src_format, enum pipe_format dst_format, VkImageAspectFlags aspect_mask, unsigned blit_param, bool clear, bool ubwc, VkSampleCountFlagBits samples) r2d_setup() argument
407 r2d_teardown(struct tu_cmd_buffer *cmd, struct tu_cs *cs) r2d_teardown() argument
414 r2d_run(struct tu_cmd_buffer *cmd, struct tu_cs *cs) r2d_run() argument
695 r3d_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool blit, uint32_t rts_mask, bool z_scale, VkSampleCountFlagBits samples) r3d_common() argument
805 r3d_coords_raw(struct tu_cs *cs, const float *coords) r3d_coords_raw() argument
820 r3d_coord_z(struct tu_cs *cs, float z) r3d_coord_z() argument
837 r3d_coords(struct tu_cs *cs, const VkOffset2D *dst, const VkOffset2D *src, const VkExtent2D *extent) r3d_coords() argument
853 r3d_clear_value(struct tu_cs *cs, enum pipe_format format, const VkClearValue *val) r3d_clear_value() argument
895 r3d_src_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, const uint32_t *tex_const, uint32_t offset_base, uint32_t offset_ubwc, VkFilter filter) r3d_src_common() argument
955 r3d_src(struct tu_cmd_buffer *cmd, struct tu_cs *cs, const struct fdl6_view *iview, uint32_t layer, VkFilter filter, enum pipe_format dst_format) r3d_src() argument
979 r3d_src_buffer(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum pipe_format format, uint64_t va, uint32_t pitch, uint32_t width, uint32_t height, enum pipe_format dst_format) r3d_src_buffer() argument
1014 r3d_src_gmem(struct tu_cmd_buffer *cmd, struct tu_cs *cs, const struct tu_image_view *iview, enum pipe_format format, enum pipe_format dst_format, uint32_t gmem_offset, uint32_t cpp) r3d_src_gmem() argument
1054 r3d_dst(struct tu_cs *cs, const struct fdl6_view *iview, uint32_t layer, enum pipe_format src_format) r3d_dst() argument
1082 r3d_dst_depth(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer) r3d_dst_depth() argument
1096 r3d_dst_stencil(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer) r3d_dst_stencil() argument
1107 r3d_dst_buffer(struct tu_cs *cs, enum pipe_format format, uint64_t va, uint32_t pitch, enum pipe_format src_format) r3d_dst_buffer() argument
1143 r3d_setup(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum pipe_format src_format, enum pipe_format dst_format, VkImageAspectFlags aspect_mask, unsigned blit_param, bool clear, bool ubwc, VkSampleCountFlagBits samples) r3d_setup() argument
1225 r3d_run(struct tu_cmd_buffer *cmd, struct tu_cs *cs) r3d_run() argument
1236 r3d_run_vis(struct tu_cmd_buffer *cmd, struct tu_cs *cs) r3d_run_vis() argument
1247 r3d_teardown(struct tu_cmd_buffer *cmd, struct tu_cs *cs) r3d_teardown() argument
1332 coords(const struct blit_ops *ops, struct tu_cs *cs, const VkOffset3D *dst, const VkOffset3D *src, const VkExtent3D *extent) coords() argument
1394 tu6_clear_lrz(struct tu_cmd_buffer *cmd, struct tu_cs *cs, struct tu_image *image, const VkClearValue *value) tu6_clear_lrz() argument
1430 tu6_dirty_lrz_fc(struct tu_cmd_buffer *cmd, struct tu_cs *cs, struct tu_image *image) tu6_dirty_lrz_fc() argument
1513 struct tu_cs *cs = &cmd->cs; tu6_blit_image() local
1699 struct tu_cs *cs = &cmd->cs; tu_copy_buffer_to_image() local
1781 struct tu_cs *cs = &cmd->cs; tu_copy_image_to_buffer() local
1886 struct tu_cs *cs = &cmd->cs; tu_copy_image_to_image() local
2099 struct tu_cs *cs = &cmd->cs; copy_buffer() local
2172 struct tu_cs *cs = &cmd->cs; tu_CmdFillBuffer() local
2208 struct tu_cs *cs = &cmd->cs; tu_CmdResolveImage2KHR() local
2248 resolve_sysmem(struct tu_cmd_buffer *cmd, struct tu_cs *cs, VkFormat vk_src_format, VkFormat vk_dst_format, const struct tu_image_view *src, const struct tu_image_view *dst, uint32_t layer_mask, uint32_t layers, const VkRect2D *rect, bool src_separate_ds, bool dst_separate_ds) resolve_sysmem() argument
2302 tu_resolve_sysmem(struct tu_cmd_buffer *cmd, struct tu_cs *cs, const struct tu_image_view *src, const struct tu_image_view *dst, uint32_t layer_mask, uint32_t layers, const VkRect2D *rect) tu_resolve_sysmem() argument
2340 struct tu_cs *cs = &cmd->cs; clear_image() local
2442 struct tu_cs *cs = &cmd->draw_cs; tu_clear_sysmem_attachments() local
2679 clear_gmem_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum pipe_format format, uint8_t clear_mask, uint32_t gmem_offset, const VkClearValue *value) clear_gmem_attachment() argument
2707 tu_emit_clear_gmem_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t attachment, VkImageAspectFlags mask, const VkClearValue *value) tu_emit_clear_gmem_attachment() argument
2741 struct tu_cs *cs = &cmd->draw_cs; tu_clear_gmem_attachments() local
2780 struct tu_cs *cs = &cmd->draw_cs; tu_CmdClearAttachments() local
2840 clear_sysmem_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, VkFormat vk_format, VkImageAspectFlags clear_mask, const VkClearValue *value, uint32_t a, bool separate_ds) clear_sysmem_attachment() argument
2885 tu_clear_sysmem_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a, const VkClearValue *value) tu_clear_sysmem_attachment() argument
2933 tu_clear_gmem_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a, const VkClearValue *value) tu_clear_gmem_attachment() argument
2950 tu_emit_blit(struct tu_cmd_buffer *cmd, struct tu_cs *cs, const struct tu_image_view *iview, const struct tu_render_pass_attachment *attachment, bool resolve, bool separate_stencil) tu_emit_blit() argument
3035 tu_begin_load_store_cond_exec(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool load) tu_begin_load_store_cond_exec() argument
3058 tu_end_load_store_cond_exec(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool load) tu_end_load_store_cond_exec() argument
3081 tu_load_gmem_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a, bool cond_exec_allowed, bool force_load) tu_load_gmem_attachment() argument
3125 store_cp_blit(struct tu_cmd_buffer *cmd, struct tu_cs *cs, const struct tu_image_view *iview, uint32_t samples, bool separate_stencil, enum pipe_format src_format, enum pipe_format dst_format, uint32_t gmem_offset, uint32_t cpp) store_cp_blit() argument
3184 store_3d_blit(struct tu_cmd_buffer *cmd, struct tu_cs *cs, const struct tu_image_view *iview, uint32_t dst_samples, bool separate_stencil, enum pipe_format src_format, enum pipe_format dst_format, const VkRect2D *render_area, uint32_t gmem_offset, uint32_t cpp) store_3d_blit() argument
3308 tu_store_gmem_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a, uint32_t gmem_a, bool cond_exec_allowed) tu_store_gmem_attachment() argument
[all...]
H A Dtu_cmd_buffer.c22 struct tu_cs *cs, in tu6_emit_event_write()
39 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1); in tu6_emit_event_write()
40 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event)); in tu6_emit_event_write()
42 tu_cs_emit_qw(cs, global_iova(cmd, seqno_dummy)); in tu6_emit_event_write()
43 tu_cs_emit(cs, 0); in tu6_emit_event_write()
58 tu_cs_emit_regs(&cmd->cs, A6XX_PC_TESSFACTOR_ADDR(.qword = cmd->device->tess_bo->iova)); in tu6_lazy_emit_tessfactor_addr()
66 struct tu_cs *cs, in tu6_emit_flushes()
84 tu6_emit_event_write(cmd_buffer, cs, PC_CCU_FLUSH_COLOR_TS); in tu6_emit_flushes()
87 tu6_emit_event_write(cmd_buffer, cs, PC_CCU_FLUSH_DEPTH_TS); in tu6_emit_flushes()
89 tu6_emit_event_write(cmd_buffer, cs, PC_CCU_INVALIDATE_COLO in tu6_emit_flushes()
21 tu6_emit_event_write(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum vgt_event_type event) tu6_emit_event_write() argument
65 tu6_emit_flushes(struct tu_cmd_buffer *cmd_buffer, struct tu_cs *cs, enum tu_cmd_flush_bits flushes) tu6_emit_flushes() argument
109 tu_emit_cache_flush(struct tu_cmd_buffer *cmd_buffer, struct tu_cs *cs) tu_emit_cache_flush() argument
119 tu_emit_cache_flush_renderpass(struct tu_cmd_buffer *cmd_buffer, struct tu_cs *cs) tu_emit_cache_flush_renderpass() argument
135 tu_emit_cache_flush_ccu(struct tu_cmd_buffer *cmd_buffer, struct tu_cs *cs, enum tu_cmd_ccu_state ccu_state) tu_emit_cache_flush_ccu() argument
185 tu6_emit_zs(struct tu_cmd_buffer *cmd, const struct tu_subpass *subpass, struct tu_cs *cs) tu6_emit_zs() argument
244 tu6_emit_mrt(struct tu_cmd_buffer *cmd, const struct tu_subpass *subpass, struct tu_cs *cs) tu6_emit_mrt() argument
300 tu6_emit_msaa(struct tu_cs *cs, VkSampleCountFlagBits vk_samples, enum a5xx_line_mode line_mode) tu6_emit_msaa() argument
326 tu6_emit_bin_size(struct tu_cs *cs, uint32_t bin_w, uint32_t bin_h, uint32_t flags) tu6_emit_bin_size() argument
346 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd, const struct tu_subpass *subpass, struct tu_cs *cs, bool binning) tu6_emit_render_cntl() argument
405 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align) tu6_emit_blit_scissor() argument
438 tu6_emit_window_scissor(struct tu_cs *cs, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2) tu6_emit_window_scissor() argument
454 tu6_emit_window_offset(struct tu_cs *cs, uint32_t x1, uint32_t y1) tu6_emit_window_offset() argument
487 tu_cs_emit_draw_state(struct tu_cs *cs, uint32_t id, struct tu_draw_state state) tu_cs_emit_draw_state() argument
629 tu6_emit_cond_for_load_stores(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t pipe, uint32_t slot, bool wfm) tu6_emit_cond_for_load_stores() argument
643 tu6_emit_tile_select(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t tx, uint32_t ty, uint32_t pipe, uint32_t slot) tu6_emit_tile_select() argument
685 tu6_emit_sysmem_resolve(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t layer_mask, uint32_t a, uint32_t gmem_a) tu6_emit_sysmem_resolve() argument
699 tu6_emit_sysmem_resolves(struct tu_cmd_buffer *cmd, struct tu_cs *cs, const struct tu_subpass *subpass) tu6_emit_sysmem_resolves() argument
747 tu6_emit_tile_load(struct tu_cmd_buffer *cmd, struct tu_cs *cs) tu6_emit_tile_load() argument
756 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs) tu6_emit_tile_store() argument
786 tu_disable_draw_states(struct tu_cmd_buffer *cmd, struct tu_cs *cs) tu_disable_draw_states() argument
799 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs) tu6_init_hw() argument
946 update_vsc_pipe(struct tu_cmd_buffer *cmd, struct tu_cs *cs) update_vsc_pipe() argument
971 emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs) emit_vsc_overflow_test() argument
1003 tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs) tu6_emit_binning_pass() argument
1202 struct tu_cs cs; tu_emit_input_attachments() local
1225 struct tu_cs *cs = &cmd->draw_cs; tu_set_input_attachments() local
1239 struct tu_cs *cs = &cmd->draw_cs; tu_emit_renderpass_begin() local
1261 tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs, struct tu_renderpass_result *autotune_result) tu6_sysmem_render_begin() argument
1296 tu6_sysmem_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs, struct tu_renderpass_result *autotune_result) tu6_sysmem_render_end() argument
1317 tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs, struct tu_renderpass_result *autotune_result) tu6_tile_render_begin() argument
1374 tu6_render_tile(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t tx, uint32_t ty, uint32_t pipe, uint32_t slot) tu6_render_tile() argument
1418 tu6_tile_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs, struct tu_renderpass_result *autotune_result) tu6_tile_render_end() argument
1882 struct tu_cs cs; tu_CmdBindVertexBuffers2EXT() local
2033 struct tu_cs *cs, state_cs; tu_CmdBindDescriptorSets() local
2192 struct tu_cs *cs = &cmd->draw_cs; tu_CmdBindTransformFeedbackBuffersEXT() local
2233 struct tu_cs *cs = &cmd->draw_cs; tu_CmdBeginTransformFeedbackEXT() local
2281 struct tu_cs *cs = &cmd->draw_cs; tu_CmdEndTransformFeedbackEXT() local
2398 struct tu_cs cs; tu_cmd_dynamic_state() local
2435 struct tu_cs *cs = &cmd->draw_cs; tu_CmdBindPipeline() local
2603 struct tu_cs cs; tu_CmdSetScissor() local
2630 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_DEPTH_BIAS, 4); tu_CmdSetDepthBias() local
2640 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_BLEND_CONSTANTS, 5); tu_CmdSetBlendConstants() local
2652 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_DEPTH_BOUNDS, 3); tu_CmdSetDepthBounds() local
2674 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK, 2); tu_CmdSetStencilCompareMask() local
2687 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK, 2); tu_CmdSetStencilWriteMask() local
2702 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_STENCIL_REFERENCE, 2); tu_CmdSetStencilReference() local
2714 struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS, 9); tu_CmdSetSampleLocationsEXT() local
4048 struct tu_cs *cs = &cmd->draw_cs; tu_CmdNextSubpass2() local
4122 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline, gl_shader_stage type, uint32_t *push_constants) tu6_emit_user_consts() argument
4149 tu6_emit_shared_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline, uint32_t *push_constants, bool compute) tu6_emit_shared_consts() argument
4209 struct tu_cs cs; tu6_emit_consts() local
4291 tu6_build_depth_plane_z_mode(struct tu_cmd_buffer *cmd, struct tu_cs *cs) tu6_build_depth_plane_z_mode() argument
4321 tu6_emit_blend(struct tu_cs *cs, struct tu_cmd_buffer *cmd) tu6_emit_blend() argument
4360 tu6_draw_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool indexed, uint32_t draw_count) tu6_draw_common() argument
4409 struct tu_cs cs; tu6_draw_common() local
4419 struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_RASTERIZER_DISCARD, 4); tu6_draw_common() local
4425 struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_GRAS_SU_CNTL, 2); tu6_draw_common() local
4430 struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_RB_DEPTH_CNTL, 2); tu6_draw_common() local
4448 struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_RB_STENCIL_CNTL, 2); tu6_draw_common() local
4456 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_VIEWPORT, 8 + 10 * cmd->state.max_viewport); tu6_draw_common() local
4462 struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_BLEND, tu6_draw_common() local
4655 struct tu_cs cs; tu6_emit_vs_params() local
4699 struct tu_cs *cs = &cmd->draw_cs; tu_CmdDraw() local
4720 struct tu_cs *cs = &cmd->draw_cs; tu_CmdDrawIndexed() local
4758 struct tu_cs *cs = &cmd->draw_cs; tu_CmdDrawIndirect() local
4785 struct tu_cs *cs = &cmd->draw_cs; tu_CmdDrawIndexedIndirect() local
4817 struct tu_cs *cs = &cmd->draw_cs; tu_CmdDrawIndirectCount() local
4852 struct tu_cs *cs = &cmd->draw_cs; tu_CmdDrawIndexedIndirectCount() local
4883 struct tu_cs *cs = &cmd->draw_cs; tu_CmdDrawIndirectByteCountEXT() local
4929 tu_emit_compute_driver_params(struct tu_cmd_buffer *cmd, struct tu_cs *cs, struct tu_pipeline *pipeline, const struct tu_dispatch_info *info) tu_emit_compute_driver_params() argument
5040 struct tu_cs *cs = &cmd->cs; tu_dispatch() local
5340 struct tu_cs *cs = &cmd->cs; write_event() local
5404 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs; tu_CmdWaitEvents2() local
5436 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs; tu_CmdBeginConditionalRenderingEXT() local
5477 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs; tu_CmdEndConditionalRenderingEXT() local
5496 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs; tu_CmdWriteBufferMarker2AMD() local
[all...]
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_cs.h35 radeon_check_space(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, unsigned needed) in radeon_check_space() argument
37 if (cs->max_dw - cs->cdw < needed) in radeon_check_space()
38 ws->cs_grow(cs, needed); in radeon_check_space()
39 return cs->cdw + needed; in radeon_check_space()
43 radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_config_reg_seq() argument
46 assert(cs->cdw + 2 + num <= cs->max_dw); in radeon_set_config_reg_seq()
48 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); in radeon_set_config_reg_seq()
49 radeon_emit(cs, (re in radeon_set_config_reg_seq()
53 radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) radeon_set_config_reg() argument
60 radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) radeon_set_context_reg_seq() argument
70 radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) radeon_set_context_reg() argument
77 radeon_set_context_reg_idx(struct radeon_cmdbuf *cs, unsigned reg, unsigned idx, unsigned value) radeon_set_context_reg_idx() argument
87 radeon_set_context_reg_rmw(struct radeon_cmdbuf *cs, unsigned reg, unsigned value, unsigned mask) radeon_set_context_reg_rmw() argument
98 radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) radeon_set_sh_reg_seq() argument
108 radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) radeon_set_sh_reg() argument
115 radeon_set_sh_reg_idx(const struct radv_physical_device *pdevice, struct radeon_cmdbuf *cs, unsigned reg, unsigned idx, unsigned value) radeon_set_sh_reg_idx() argument
132 gfx10_set_sh_reg_idx3(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) gfx10_set_sh_reg_idx3() argument
143 radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) radeon_set_uconfig_reg_seq() argument
153 radeon_set_uconfig_reg_seq_perfctr(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) radeon_set_uconfig_reg_seq_perfctr() argument
163 radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) radeon_set_uconfig_reg() argument
170 radeon_set_uconfig_reg_idx(const struct radv_physical_device *pdevice, struct radeon_cmdbuf *cs, unsigned reg, unsigned idx, unsigned value) radeon_set_uconfig_reg_idx() argument
190 struct radeon_cmdbuf *cs = cmd_buffer->cs; radeon_set_perfctr_reg() local
208 radeon_set_privileged_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) radeon_set_privileged_config_reg() argument
[all...]
H A Dsi_cmd_buffer.c37 struct radeon_cmdbuf *cs, unsigned raster_config, in si_write_harvested_raster_configs()
50 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX, in si_write_harvested_raster_configs()
54 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, in si_write_harvested_raster_configs()
57 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]); in si_write_harvested_raster_configs()
62 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX, in si_write_harvested_raster_configs()
66 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, in si_write_harvested_raster_configs()
71 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); in si_write_harvested_raster_configs()
75 si_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs) in si_emit_compute() argument
79 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3); in si_emit_compute()
80 radeon_emit(cs, in si_emit_compute()
36 si_write_harvested_raster_configs(struct radv_physical_device *physical_device, struct radeon_cmdbuf *cs, unsigned raster_config, unsigned raster_config_1) si_write_harvested_raster_configs() argument
176 si_set_raster_config(struct radv_physical_device *physical_device, struct radeon_cmdbuf *cs) si_set_raster_config() argument
197 si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) si_emit_graphics() argument
633 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, AMD_IP_GFX); cik_create_gfx_config() local
717 si_write_scissors(struct radeon_cmdbuf *cs, int first, int count, const VkRect2D *scissors, const VkViewport *viewports, unsigned rast_prim, float line_width) si_write_scissors() argument
927 si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, bool is_mec, unsigned event, unsigned event_flags, unsigned dst_sel, unsigned data_sel, uint64_t va, uint32_t new_fence, uint64_t gfx9_eop_bug_va) si_cs_emit_write_event_eop() argument
1014 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va, uint32_t ref, uint32_t mask) radv_cp_wait_mem() argument
1029 si_emit_acquire_mem(struct radeon_cmdbuf *cs, bool is_mec, bool is_gfx9, unsigned cp_coher_cntl) si_emit_acquire_mem() argument
1051 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, uint32_t *flush_cnt, uint64_t flush_va, bool is_mec, enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va) gfx10_cs_emit_cache_flush() argument
1232 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, uint32_t *flush_cnt, uint64_t flush_va, bool is_mec, enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va) si_cs_emit_cache_flush() argument
1532 si_cs_emit_cp_dma(struct radv_device *device, struct radeon_cmdbuf *cs, bool predicating, uint64_t dst_va, uint64_t src_va, unsigned size, unsigned flags) si_cs_emit_cp_dma() argument
1594 struct radeon_cmdbuf *cs = cmd_buffer->cs; si_emit_cp_dma() local
1620 si_cs_cp_dma_prefetch(const struct radv_device *device, struct radeon_cmdbuf *cs, uint64_t va, unsigned size, bool predicating) si_cs_cp_dma_prefetch() argument
1895 radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples) radv_emit_default_sample_locations() argument
[all...]
H A Dradv_sqtt.c64 radv_emit_wait_for_idle(struct radv_device *device, struct radeon_cmdbuf *cs, int family) in radv_emit_wait_for_idle() argument
68 cs, device->physical_device->rad_info.gfx_level, NULL, 0, in radv_emit_wait_for_idle()
79 radv_emit_thread_trace_start(struct radv_device *device, struct radeon_cmdbuf *cs, in radv_emit_thread_trace_start() argument
97 cs, R_030800_GRBM_GFX_INDEX, in radv_emit_thread_trace_start()
103 cs, R_008D04_SQ_THREAD_TRACE_BUF0_SIZE, in radv_emit_thread_trace_start()
106 radeon_set_privileged_config_reg(cs, R_008D00_SQ_THREAD_TRACE_BUF0_BASE, shifted_va); in radv_emit_thread_trace_start()
109 cs, R_008D14_SQ_THREAD_TRACE_MASK, in radv_emit_thread_trace_start()
130 radeon_set_privileged_config_reg(cs, R_008D18_SQ_THREAD_TRACE_TOKEN_MASK, in radv_emit_thread_trace_start()
134 radeon_set_privileged_config_reg(cs, R_008D1C_SQ_THREAD_TRACE_CTRL, in radv_emit_thread_trace_start()
138 radeon_set_uconfig_reg(cs, R_030CDC_SQ_THREAD_TRACE_BASE in radv_emit_thread_trace_start()
225 radv_copy_thread_trace_info_regs(struct radv_device *device, struct radeon_cmdbuf *cs, unsigned se_index) radv_copy_thread_trace_info_regs() argument
256 radv_emit_thread_trace_stop(struct radv_device *device, struct radeon_cmdbuf *cs, enum radv_queue_family qf) radv_emit_thread_trace_stop() argument
342 struct radeon_cmdbuf *cs = cmd_buffer->cs; radv_emit_thread_trace_userdata() local
368 radv_emit_spi_config_cntl(struct radv_device *device, struct radeon_cmdbuf *cs, bool enable) radv_emit_spi_config_cntl() argument
388 radv_emit_inhibit_clockgating(struct radv_device *device, struct radeon_cmdbuf *cs, bool inhibit) radv_emit_inhibit_clockgating() argument
534 struct radeon_cmdbuf *cs; radv_begin_thread_trace() local
603 struct radeon_cmdbuf *cs; radv_end_thread_trace() local
[all...]
H A Dradv_sdma_copy_image.c90 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, align(8, ib_pad_dw_mask + 1)); in radv_sdma_v4_v5_copy_image_to_buffer()
96 radeon_emit(cmd_buffer->cs, 0x00000000); in radv_sdma_v4_v5_copy_image_to_buffer()
100 radeon_emit(cmd_buffer->cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY, in radv_sdma_v4_v5_copy_image_to_buffer()
102 radeon_emit(cmd_buffer->cs, bytes); in radv_sdma_v4_v5_copy_image_to_buffer()
103 radeon_emit(cmd_buffer->cs, 0); in radv_sdma_v4_v5_copy_image_to_buffer()
104 radeon_emit(cmd_buffer->cs, src_address); in radv_sdma_v4_v5_copy_image_to_buffer()
105 radeon_emit(cmd_buffer->cs, src_address >> 32); in radv_sdma_v4_v5_copy_image_to_buffer()
106 radeon_emit(cmd_buffer->cs, dst_address); in radv_sdma_v4_v5_copy_image_to_buffer()
107 radeon_emit(cmd_buffer->cs, dst_address >> 32); in radv_sdma_v4_v5_copy_image_to_buffer()
109 while (cmd_buffer->cs in radv_sdma_v4_v5_copy_image_to_buffer()
[all...]
/third_party/backends/backend/
H A Dcanon_pp.c87 static SANE_Status fix_weights_file(CANONP_Scanner *cs);
89 static SANE_Status detect_mode(CANONP_Scanner *cs);
510 CANONP_Scanner *cs; in sane_open() local
534 cs = first_dev; in sane_open()
535 while((cs != NULL) && strcmp(cs->params.port->name, name)) in sane_open()
536 cs = cs->next; in sane_open()
540 if ((cs == NULL) || (cs in sane_open()
697 CANONP_Scanner *cs = ((CANONP_Scanner *)h); sane_get_option_descriptor() local
735 CANONP_Scanner *cs = ((CANONP_Scanner *)h); sane_control_option() local
924 CANONP_Scanner *cs = ((CANONP_Scanner *)h); sane_get_parameters() local
1023 CANONP_Scanner *cs = ((CANONP_Scanner *)h); sane_start() local
1140 CANONP_Scanner *cs = ((CANONP_Scanner *)h); sane_read() local
1380 CANONP_Scanner *cs = ((CANONP_Scanner *)h); sane_cancel() local
1411 CANONP_Scanner *cs = ((CANONP_Scanner *)h); sane_close() local
1566 CANONP_Scanner *cs = NULL; init_device() local
1788 fix_weights_file(CANONP_Scanner *cs) fix_weights_file() argument
1905 detect_mode(CANONP_Scanner *cs) detect_mode() argument
[all...]
/third_party/mesa3d/src/gallium/drivers/r600/
H A Dr600_cs.h45 struct radeon_cmdbuf *cs, in radeon_cs_memory_below_limit()
48 vram += (uint64_t)cs->used_vram_kb * 1024; in radeon_cs_memory_below_limit()
49 gtt += (uint64_t)cs->used_gart_kb * 1024; in radeon_cs_memory_below_limit()
76 &ring->cs, rbo->buf, in radeon_add_to_buffer_list()
106 !radeon_cs_memory_below_limit(rctx->screen, &ring->cs, in radeon_add_to_buffer_list_check_mem()
118 struct radeon_cmdbuf *cs = &ring->cs; in r600_emit_reloc() local
123 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_reloc()
124 radeon_emit(cs, reloc); in r600_emit_reloc()
128 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigne argument
44 radeon_cs_memory_below_limit(struct r600_common_screen *screen, struct radeon_cmdbuf *cs, uint64_t vram, uint64_t gtt) radeon_cs_memory_below_limit() argument
136 radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) radeon_set_config_reg() argument
142 radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) radeon_set_context_reg_seq() argument
150 radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) radeon_set_context_reg() argument
156 radeon_set_context_reg_idx(struct radeon_cmdbuf *cs, unsigned reg, unsigned idx, unsigned value) radeon_set_context_reg_idx() argument
167 radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) radeon_set_sh_reg_seq() argument
175 radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) radeon_set_sh_reg() argument
181 radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) radeon_set_uconfig_reg_seq() argument
189 radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) radeon_set_uconfig_reg() argument
195 radeon_set_uconfig_reg_idx(struct radeon_cmdbuf *cs, unsigned reg, unsigned idx, unsigned value) radeon_set_uconfig_reg_idx() argument
[all...]
H A Dcayman_msaa.c144 static void cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples) in cayman_emit_msaa_sample_locs() argument
149 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0); in cayman_emit_msaa_sample_locs()
150 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0); in cayman_emit_msaa_sample_locs()
151 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0); in cayman_emit_msaa_sample_locs()
152 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0); in cayman_emit_msaa_sample_locs()
155 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]); in cayman_emit_msaa_sample_locs()
156 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]); in cayman_emit_msaa_sample_locs()
157 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]); in cayman_emit_msaa_sample_locs()
158 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]); in cayman_emit_msaa_sample_locs()
161 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_ in cayman_emit_msaa_sample_locs()
205 cayman_emit_msaa_state(struct radeon_cmdbuf *cs, int nr_samples, int ps_iter_samples, int overrast_samples) cayman_emit_msaa_state() argument
[all...]
H A Dr600_hw_context.c37 if (radeon_emitted(&ctx->b.dma.cs, 0)) in r600_need_cs_space()
40 if (!radeon_cs_memory_below_limit(ctx->b.screen, &ctx->b.gfx.cs, in r600_need_cs_space()
87 if (!ctx->b.ws->cs_check_space(&ctx->b.gfx.cs, num_dw)) { in r600_need_cs_space()
94 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; in r600_flush_emit() local
125 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
126 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); in r600_flush_emit()
130 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
131 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CS_PARTIAL_FLUSH) | EVENT_INDEX(4)); in r600_flush_emit()
138 radeon_set_config_reg(cs, R_008040_WAIT_UNTI in r600_flush_emit()
263 struct radeon_cmdbuf *cs = &ctx->b.gfx.cs; r600_context_gfx_flush() local
439 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; r600_emit_pfp_sync_me() local
504 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; r600_cp_dma_copy_buffer() local
586 struct radeon_cmdbuf *cs = &rctx->b.dma.cs; r600_dma_copy_buffer() local
[all...]
/third_party/ffmpeg/libavutil/
H A Dcamellia.c188 static void generate_round_keys(AVCAMELLIA *cs, uint64_t Kl[2], uint64_t Kr[2], uint64_t Ka[2], uint64_t Kb[2]) in generate_round_keys() argument
196 cs->Kw[0] = Kl[0]; in generate_round_keys()
197 cs->Kw[1] = Kl[1]; in generate_round_keys()
198 if (cs->key_bits == 128) { in generate_round_keys()
201 cs->K[2*i] = d[0]; in generate_round_keys()
202 cs->K[2*i+1] = d[1]; in generate_round_keys()
205 cs->K[9] = d[1]; in generate_round_keys()
207 cs->Ke[0] = d[0]; in generate_round_keys()
208 cs->Ke[1] = d[1]; in generate_round_keys()
210 cs in generate_round_keys()
236 camellia_encrypt(AVCAMELLIA *cs, uint8_t *dst, const uint8_t *src) camellia_encrypt() argument
281 camellia_decrypt(AVCAMELLIA *cs, uint8_t *dst, const uint8_t *src, uint8_t *iv) camellia_decrypt() argument
356 av_camellia_init(AVCAMELLIA *cs, const uint8_t *key, int key_bits) av_camellia_init() argument
397 av_camellia_crypt(AVCAMELLIA *cs, uint8_t *dst, const uint8_t *src, int count, uint8_t *iv, int decrypt) av_camellia_crypt() argument
[all...]
/third_party/mesa3d/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_cs.c179 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(rcs); in radv_amdgpu_cs_destroy() local
181 if (cs->ib_buffer) in radv_amdgpu_cs_destroy()
182 cs->ws->base.buffer_destroy(&cs->ws->base, cs->ib_buffer); in radv_amdgpu_cs_destroy()
184 free(cs->base.buf); in radv_amdgpu_cs_destroy()
186 for (unsigned i = 0; i < cs->num_old_ib_buffers; ++i) in radv_amdgpu_cs_destroy()
187 cs->ws->base.buffer_destroy(&cs->ws->base, cs in radv_amdgpu_cs_destroy()
202 radv_amdgpu_init_cs(struct radv_amdgpu_cs *cs, enum amd_ip_type ip_type) radv_amdgpu_init_cs() argument
226 struct radv_amdgpu_cs *cs; radv_amdgpu_cs_create() local
281 get_nop_packet(struct radv_amdgpu_cs *cs) get_nop_packet() argument
302 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs); radv_amdgpu_cs_grow() local
427 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs); radv_amdgpu_cs_finalize() local
462 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs); radv_amdgpu_cs_reset() local
503 radv_amdgpu_cs_find_buffer(struct radv_amdgpu_cs *cs, uint32_t bo) radv_amdgpu_cs_find_buffer() argument
525 radv_amdgpu_cs_add_buffer_internal(struct radv_amdgpu_cs *cs, uint32_t bo, uint8_t priority) radv_amdgpu_cs_add_buffer_internal() argument
558 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs); radv_amdgpu_cs_add_virtual_buffer() local
607 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs); radv_amdgpu_cs_add_buffer() local
772 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)cs_array[0]; radv_amdgpu_get_bo_list() local
786 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)cs_array[i]; radv_amdgpu_get_bo_list() local
811 struct radv_amdgpu_cs *cs; radv_amdgpu_get_bo_list() local
908 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]); radv_amdgpu_winsys_cs_submit_chained() local
1018 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]); radv_amdgpu_winsys_cs_submit_fallback() local
1080 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]); radv_amdgpu_winsys_cs_submit_sysmem() local
1468 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs; radv_amdgpu_winsys_get_cpu_addr() local
1502 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs; radv_amdgpu_winsys_cs_dump() local
[all...]
/third_party/mesa3d/src/gallium/winsys/amdgpu/drm/
H A Damdgpu_cs.c254 struct amdgpu_cs *cs = amdgpu_cs(rcs); in amdgpu_cs_get_next_fence() local
257 if (cs->noop) in amdgpu_cs_get_next_fence()
260 if (cs->next_fence) { in amdgpu_cs_get_next_fence()
261 amdgpu_fence_reference(&fence, cs->next_fence); in amdgpu_cs_get_next_fence()
265 fence = amdgpu_fence_create(cs->ctx, in amdgpu_cs_get_next_fence()
266 cs->csc->ib[IB_MAIN].ip_type); in amdgpu_cs_get_next_fence()
270 amdgpu_fence_reference(&cs->next_fence, fence); in amdgpu_cs_get_next_fence()
367 * recoveries), we can use the rejected cs count as a quick first check. in amdgpu_ctx_query_reset_status()
421 static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context *cs) in amdgpu_cs_has_user_fence() argument
423 return cs in amdgpu_cs_has_user_fence()
431 amdgpu_cs_epilog_dws(struct amdgpu_cs *cs) amdgpu_cs_epilog_dws() argument
439 amdgpu_lookup_buffer(struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo *bo, struct amdgpu_cs_buffer *buffers, unsigned num_buffers) amdgpu_lookup_buffer() argument
468 amdgpu_lookup_buffer_any_type(struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo *bo) amdgpu_lookup_buffer_any_type() argument
488 amdgpu_do_add_real_buffer(struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo *bo) amdgpu_do_add_real_buffer() argument
527 amdgpu_lookup_or_add_real_buffer(struct radeon_cmdbuf *rcs, struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo *bo) amdgpu_lookup_or_add_real_buffer() argument
549 amdgpu_lookup_or_add_slab_buffer(struct radeon_cmdbuf *rcs, struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo *bo) amdgpu_lookup_or_add_slab_buffer() argument
597 amdgpu_lookup_or_add_sparse_buffer(struct radeon_cmdbuf *rcs, struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo *bo) amdgpu_lookup_or_add_sparse_buffer() argument
661 struct amdgpu_cs_context *cs = (struct amdgpu_cs_context*)rcs->csc; amdgpu_cs_add_buffer() local
711 amdgpu_ib_new_buffer(struct amdgpu_winsys *ws, struct amdgpu_ib *ib, struct amdgpu_cs *cs) amdgpu_ib_new_buffer() argument
771 amdgpu_get_new_ib(struct amdgpu_winsys *ws, struct radeon_cmdbuf *rcs, struct amdgpu_ib *ib, struct amdgpu_cs *cs) amdgpu_get_new_ib() argument
849 amdgpu_init_cs_context(struct amdgpu_winsys *ws, struct amdgpu_cs_context *cs, enum amd_ip_type ip_type) amdgpu_init_cs_context() argument
919 amdgpu_cs_context_cleanup(struct amdgpu_winsys *ws, struct amdgpu_cs_context *cs) amdgpu_cs_context_cleanup() argument
943 amdgpu_destroy_cs_context(struct amdgpu_winsys *ws, struct amdgpu_cs_context *cs) amdgpu_destroy_cs_context() argument
965 struct amdgpu_cs *cs; amdgpu_cs_create() local
1030 amdgpu_cs_set_preamble(struct radeon_cmdbuf *cs, const uint32_t *preamble_ib, unsigned preamble_num_dw, bool preamble_changed) amdgpu_cs_set_preamble() argument
1041 struct amdgpu_cs *cs = amdgpu_cs(rcs); amdgpu_cs_setup_preemption() local
1095 struct amdgpu_cs *cs = amdgpu_cs(rcs); amdgpu_cs_check_space() local
1183 struct amdgpu_cs_context *cs = amdgpu_cs(rcs)->csc; amdgpu_cs_get_buffer_list() local
1218 struct amdgpu_cs_context *cs = acs->csc; is_noop_fence_dependency() local
1241 struct amdgpu_cs_context *cs = acs->csc; amdgpu_cs_add_fence_dependency() local
1255 amdgpu_add_bo_fence_dependencies(struct amdgpu_cs *acs, struct amdgpu_cs_context *cs, struct amdgpu_cs_buffer *buffer) amdgpu_add_bo_fence_dependencies() argument
1337 amdgpu_add_fence_dependencies_bo_list(struct amdgpu_cs *acs, struct amdgpu_cs_context *cs, struct pipe_fence_handle *fence, unsigned num_buffers, struct amdgpu_cs_buffer *buffers) amdgpu_add_fence_dependencies_bo_list() argument
1355 amdgpu_add_fence_dependencies_bo_lists(struct amdgpu_cs *acs, struct amdgpu_cs_context *cs) amdgpu_add_fence_dependencies_bo_lists() argument
1367 struct amdgpu_cs_context *cs = acs->csc; amdgpu_cs_add_syncobj_signal() local
1379 amdgpu_add_sparse_backing_buffers(struct amdgpu_cs_context *cs) amdgpu_add_sparse_backing_buffers() argument
1411 struct amdgpu_cs_context *cs = acs->cst; amdgpu_cs_submit_ib() local
1684 struct amdgpu_cs *cs = amdgpu_cs(rcs); amdgpu_cs_sync_flush() local
1694 struct amdgpu_cs *cs = amdgpu_cs(rcs); amdgpu_cs_flush() local
1822 struct amdgpu_cs *cs = amdgpu_cs(rcs); amdgpu_cs_destroy() local
1843 struct amdgpu_cs *cs = amdgpu_cs(rcs); amdgpu_bo_is_referenced() local
[all...]
/third_party/mesa3d/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_cs.c37 cs_add_buffer(cs, buf, read_domain, write_domain) adds a new relocation and
51 cs_write_reloc(cs, buf) just writes a reloc that has been added using
132 csc->cs.chunks = (uint64_t)(uintptr_t)csc->chunk_array; in radeon_init_cs_context()
183 struct radeon_drm_cs *cs; in radeon_drm_cs_create() local
185 cs = CALLOC_STRUCT(radeon_drm_cs); in radeon_drm_cs_create()
186 if (!cs) { in radeon_drm_cs_create()
189 util_queue_fence_init(&cs->flush_completed); in radeon_drm_cs_create()
191 cs->ws = ws; in radeon_drm_cs_create()
192 cs->flush_cs = flush; in radeon_drm_cs_create()
193 cs in radeon_drm_cs_create()
219 radeon_drm_cs_set_preamble(struct radeon_cmdbuf *cs, const uint32_t *preamble_ib, unsigned preamble_num_dw, bool preamble_changed) radeon_drm_cs_set_preamble() argument
264 radeon_lookup_or_add_real_buffer(struct radeon_drm_cs *cs, struct radeon_bo *bo) radeon_lookup_or_add_real_buffer() argument
322 radeon_lookup_or_add_slab_buffer(struct radeon_drm_cs *cs, struct radeon_bo *bo) radeon_lookup_or_add_slab_buffer() argument
374 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); radeon_drm_cs_add_buffer() local
422 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); radeon_drm_cs_lookup_buffer() local
429 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); radeon_drm_cs_validate() local
475 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); radeon_drm_cs_get_buffer_list() local
525 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); radeon_drm_cs_sync_flush() local
586 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); radeon_drm_cs_flush() local
744 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); radeon_drm_cs_destroy() local
764 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); radeon_bo_is_referenced() local
790 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); radeon_cs_create_fence() local
823 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); radeon_drm_cs_get_next_fence() local
840 radeon_drm_cs_add_fence_dependency(struct radeon_cmdbuf *cs, struct pipe_fence_handle *fence, unsigned dependency_flags) radeon_drm_cs_add_fence_dependency() argument
[all...]
/third_party/libdrm/radeon/
H A Dradeon_cs_gem.c74 struct drm_radeon_cs cs; member
94 * Returns a free id for cs.
172 static int cs_gem_write_reloc(struct radeon_cs_int *cs, in cs_gem_write_reloc() argument
179 struct cs_gem *csg = (struct cs_gem*)cs; in cs_gem_write_reloc()
200 if this bo is for sure not in this cs.*/ in cs_gem_write_reloc()
201 if ((atomic_read((atomic_t *)radeon_gem_get_reloc_in_cs(bo)) & cs->id)) { in cs_gem_write_reloc()
205 for(i = cs->crelocs; i != 0;) { in cs_gem_write_reloc()
234 radeon_cs_write_dword((struct radeon_cs *)cs, 0xc0001000); in cs_gem_write_reloc()
235 radeon_cs_write_dword((struct radeon_cs *)cs, idx); in cs_gem_write_reloc()
255 cs in cs_gem_write_reloc()
276 cs_gem_begin(struct radeon_cs_int *cs, uint32_t ndw, const char *file, const char *func, int line) cs_gem_begin() argument
311 cs_gem_end(struct radeon_cs_int *cs, const char *file, const char *func, int line) cs_gem_end() argument
337 cs_gem_dump_bof(struct radeon_cs_int *cs) cs_gem_dump_bof() argument
424 cs_gem_emit(struct radeon_cs_int *cs) cs_gem_emit() argument
461 cs_gem_destroy(struct radeon_cs_int *cs) cs_gem_destroy() argument
473 cs_gem_erase(struct radeon_cs_int *cs) cs_gem_erase() argument
497 cs_gem_need_flush(struct radeon_cs_int *cs) cs_gem_need_flush() argument
502 cs_gem_print(struct radeon_cs_int *cs, FILE *file) cs_gem_print() argument
[all...]
H A Dradeon_cs.h68 extern int radeon_cs_begin(struct radeon_cs *cs,
72 extern int radeon_cs_end(struct radeon_cs *cs,
76 extern int radeon_cs_emit(struct radeon_cs *cs);
77 extern int radeon_cs_destroy(struct radeon_cs *cs);
78 extern int radeon_cs_erase(struct radeon_cs *cs);
79 extern int radeon_cs_need_flush(struct radeon_cs *cs);
80 extern void radeon_cs_print(struct radeon_cs *cs, FILE *file);
81 extern void radeon_cs_set_limit(struct radeon_cs *cs, uint32_t domain, uint32_t limit);
82 extern void radeon_cs_space_set_flush(struct radeon_cs *cs, void (*fn)(void *), void *data);
83 extern int radeon_cs_write_reloc(struct radeon_cs *cs,
115 radeon_cs_write_dword(struct radeon_cs *cs, uint32_t dword) radeon_cs_write_dword() argument
123 radeon_cs_write_qword(struct radeon_cs *cs, uint64_t qword) radeon_cs_write_qword() argument
132 radeon_cs_write_table(struct radeon_cs *cs, const void *data, uint32_t size) radeon_cs_write_table() argument
[all...]
H A Dradeon_cs.c14 radeon_cs_write_reloc(struct radeon_cs *cs, struct radeon_bo *bo, in radeon_cs_write_reloc() argument
18 struct radeon_cs_int *csi = (struct radeon_cs_int *)cs; in radeon_cs_write_reloc()
28 radeon_cs_begin(struct radeon_cs *cs, uint32_t ndw, in radeon_cs_begin() argument
31 struct radeon_cs_int *csi = (struct radeon_cs_int *)cs; in radeon_cs_begin()
36 radeon_cs_end(struct radeon_cs *cs, in radeon_cs_end() argument
39 struct radeon_cs_int *csi = (struct radeon_cs_int *)cs; in radeon_cs_end()
43 drm_public int radeon_cs_emit(struct radeon_cs *cs) in radeon_cs_emit() argument
45 struct radeon_cs_int *csi = (struct radeon_cs_int *)cs; in radeon_cs_emit()
49 drm_public int radeon_cs_destroy(struct radeon_cs *cs) in radeon_cs_destroy() argument
51 struct radeon_cs_int *csi = (struct radeon_cs_int *)cs; in radeon_cs_destroy()
55 radeon_cs_erase(struct radeon_cs *cs) radeon_cs_erase() argument
61 radeon_cs_need_flush(struct radeon_cs *cs) radeon_cs_need_flush() argument
67 radeon_cs_print(struct radeon_cs *cs, FILE *file) radeon_cs_print() argument
74 radeon_cs_set_limit(struct radeon_cs *cs, uint32_t domain, uint32_t limit) radeon_cs_set_limit() argument
83 radeon_cs_space_set_flush(struct radeon_cs *cs, void (*fn)(void *), void *data) radeon_cs_space_set_flush() argument
91 radeon_cs_get_id(struct radeon_cs *cs) radeon_cs_get_id() argument
[all...]
/third_party/mesa3d/src/gallium/drivers/etnaviv/
H A Detnaviv_state.c54 struct compiled_stencil_ref *cs = &ctx->stencil_ref; in etna_set_stencil_ref() local
59 cs->PE_STENCIL_CONFIG[i] = in etna_set_stencil_ref()
61 cs->PE_STENCIL_CONFIG_EXT[i] = in etna_set_stencil_ref()
135 struct compiled_framebuffer_state *cs = &ctx->framebuffer; in etna_set_framebuffer_state() local
160 cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT_EXT(fmt) | in etna_set_framebuffer_state()
163 cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT(fmt); in etna_set_framebuffer_state()
168 cs->PE_COLOR_FORMAT |= in etna_set_framebuffer_state()
173 cs->PE_COLOR_FORMAT |= COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW); in etna_set_framebuffer_state()
195 cs->PE_PIPE_COLOR_ADDR[i] = cbuf->reloc[i]; in etna_set_framebuffer_state()
196 cs in etna_set_framebuffer_state()
409 struct compiled_viewport_state *cs = &ctx->viewport; etna_set_viewport_states() local
459 struct compiled_set_vertex_buffer *cs = &so->cvb[idx]; etna_set_vertex_buffers() local
534 struct compiled_vertex_elements_state *cs = CALLOC_STRUCT(compiled_vertex_elements_state); etna_vertex_elements_state_create() local
[all...]
/third_party/lwip/src/netif/ppp/
H A Dvj.c23 * Modified June 1993 by Paul Mackerras, paulus@cs.anu.edu.au,
164 struct cstate *cs = comp->last_cs->cs_next; in vj_compress_tcp() local
221 if (!ip4_addr_cmp(&ip->src, &cs->cs_ip.src) in vj_compress_tcp()
222 || !ip4_addr_cmp(&ip->dest, &cs->cs_ip.dest) in vj_compress_tcp()
223 || (*(struct vj_u32_t*)th).v != (((struct vj_u32_t*)&cs->cs_ip)[IPH_HL(&cs->cs_ip)]).v) { in vj_compress_tcp()
240 lcs = cs; cs = cs->cs_next; in vj_compress_tcp()
242 if (ip4_addr_cmp(&ip->src, &cs in vj_compress_tcp()
462 struct cstate *cs; vj_uncompress_uncomp() local
501 struct cstate *cs; vj_uncompress_tcp() local
[all...]
/third_party/python/Python/
H A Dcondvar.h109 PyMUTEX_INIT(PyMUTEX_T *cs) in PyMUTEX_INIT() argument
111 InitializeCriticalSection(cs); in PyMUTEX_INIT()
116 PyMUTEX_FINI(PyMUTEX_T *cs) in PyMUTEX_FINI() argument
118 DeleteCriticalSection(cs); in PyMUTEX_FINI()
123 PyMUTEX_LOCK(PyMUTEX_T *cs) in PyMUTEX_LOCK() argument
125 EnterCriticalSection(cs); in PyMUTEX_LOCK()
130 PyMUTEX_UNLOCK(PyMUTEX_T *cs) in PyMUTEX_UNLOCK() argument
132 LeaveCriticalSection(cs); in PyMUTEX_UNLOCK()
161 _PyCOND_WAIT_MS(PyCOND_T *cv, PyMUTEX_T *cs, DWORD ms) in _PyCOND_WAIT_MS() argument
165 PyMUTEX_UNLOCK(cs); in _PyCOND_WAIT_MS()
192 PyCOND_WAIT(PyCOND_T *cv, PyMUTEX_T *cs) PyCOND_WAIT() argument
199 PyCOND_TIMEDWAIT(PyCOND_T *cv, PyMUTEX_T *cs, long long us) PyCOND_TIMEDWAIT() argument
236 PyMUTEX_INIT(PyMUTEX_T *cs) PyMUTEX_INIT() argument
243 PyMUTEX_FINI(PyMUTEX_T *cs) PyMUTEX_FINI() argument
249 PyMUTEX_LOCK(PyMUTEX_T *cs) PyMUTEX_LOCK() argument
256 PyMUTEX_UNLOCK(PyMUTEX_T *cs) PyMUTEX_UNLOCK() argument
276 PyCOND_WAIT(PyCOND_T *cv, PyMUTEX_T *cs) PyCOND_WAIT() argument
285 PyCOND_TIMEDWAIT(PyCOND_T *cv, PyMUTEX_T *cs, long long us) PyCOND_TIMEDWAIT() argument
[all...]
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dradeon_vcn.c29 void rvcn_sq_header(struct radeon_cmdbuf *cs, in rvcn_sq_header() argument
34 radeon_emit(cs, RADEON_VCN_SIGNATURE_SIZE); in rvcn_sq_header()
35 radeon_emit(cs, RADEON_VCN_SIGNATURE); in rvcn_sq_header()
36 sq->ib_checksum = &cs->current.buf[cs->current.cdw]; in rvcn_sq_header()
37 radeon_emit(cs, 0); in rvcn_sq_header()
38 sq->ib_total_size_in_dw = &cs->current.buf[cs->current.cdw]; in rvcn_sq_header()
39 radeon_emit(cs, 0); in rvcn_sq_header()
42 radeon_emit(cs, RADEON_VCN_ENGINE_INFO_SIZ in rvcn_sq_header()
49 rvcn_sq_tail(struct radeon_cmdbuf *cs, struct rvcn_sq_var *sq) rvcn_sq_tail() argument
[all...]
/third_party/vixl/test/aarch32/
H A Dtest-assembler-cond-rdlow-operand-imm8-in-it-block-t32.cc98 {{cs, r6, 221}, true, cs, "cs r6 221", "cs_r6_221"},
99 {{cs, r3, 100}, true, cs, "cs r3 100", "cs_r3_100"},
102 {{cs, r7, 201}, true, cs, "cs r7 201", "cs_r7_201"},
111 {{cs, r
[all...]

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