Lines Matching refs:cs
144 static void cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples)
149 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
150 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
151 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
152 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
155 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
156 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
157 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
158 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
161 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
162 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
163 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
164 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
167 radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
168 radeon_emit(cs, cm_sample_locs_8x[0]);
169 radeon_emit(cs, cm_sample_locs_8x[4]);
170 radeon_emit(cs, 0);
171 radeon_emit(cs, 0);
172 radeon_emit(cs, cm_sample_locs_8x[1]);
173 radeon_emit(cs, cm_sample_locs_8x[5]);
174 radeon_emit(cs, 0);
175 radeon_emit(cs, 0);
176 radeon_emit(cs, cm_sample_locs_8x[2]);
177 radeon_emit(cs, cm_sample_locs_8x[6]);
178 radeon_emit(cs, 0);
179 radeon_emit(cs, 0);
180 radeon_emit(cs, cm_sample_locs_8x[3]);
181 radeon_emit(cs, cm_sample_locs_8x[7]);
184 radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
185 radeon_emit(cs, cm_sample_locs_16x[0]);
186 radeon_emit(cs, cm_sample_locs_16x[4]);
187 radeon_emit(cs, cm_sample_locs_16x[8]);
188 radeon_emit(cs, cm_sample_locs_16x[12]);
189 radeon_emit(cs, cm_sample_locs_16x[1]);
190 radeon_emit(cs, cm_sample_locs_16x[5]);
191 radeon_emit(cs, cm_sample_locs_16x[9]);
192 radeon_emit(cs, cm_sample_locs_16x[13]);
193 radeon_emit(cs, cm_sample_locs_16x[2]);
194 radeon_emit(cs, cm_sample_locs_16x[6]);
195 radeon_emit(cs, cm_sample_locs_16x[10]);
196 radeon_emit(cs, cm_sample_locs_16x[14]);
197 radeon_emit(cs, cm_sample_locs_16x[3]);
198 radeon_emit(cs, cm_sample_locs_16x[7]);
199 radeon_emit(cs, cm_sample_locs_16x[11]);
200 radeon_emit(cs, cm_sample_locs_16x[15]);
205 void cayman_emit_msaa_state(struct radeon_cmdbuf *cs, int nr_samples,
223 cayman_emit_msaa_sample_locs(cs, nr_samples);
239 radeon_set_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
240 radeon_emit(cs, sc_line_cntl |
242 radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
247 radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
254 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
258 radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
262 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
266 radeon_set_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
267 radeon_emit(cs, sc_line_cntl); /* CM_R_028BDC_PA_SC_LINE_CNTL */
268 radeon_emit(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
270 radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
273 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,