Lines Matching refs:cs
586 struct tu_cs *cs,
595 tu_cs_emit_pkt7(cs, CP_MEM_TO_MEM, 5);
598 tu_cs_emit(cs, mem_to_mem_flags);
599 tu_cs_emit_qw(cs, write_iova);
600 tu_cs_emit_qw(cs, src_iova);
605 struct tu_cs *cs,
623 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
635 tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
636 tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
638 tu_cs_emit_qw(cs, available_iova);
639 tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(0x1));
640 tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0));
641 tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
663 copy_query_value_gpu(cmdbuf, cs, result_iova, buffer_iova,
673 tu_cs_reserve(cs, 7 + 6);
674 tu_cs_emit_pkt7(cs, CP_COND_EXEC, 6);
675 tu_cs_emit_qw(cs, available_iova);
676 tu_cs_emit_qw(cs, available_iova);
677 tu_cs_emit(cs, CP_COND_EXEC_4_REF(0x2));
678 tu_cs_emit(cs, 6); /* Cond execute the next 6 DWORDS */
681 copy_query_value_gpu(cmdbuf, cs, result_iova, buffer_iova,
688 copy_query_value_gpu(cmdbuf, cs, available_iova, buffer_iova,
707 struct tu_cs *cs = &cmdbuf->cs;
716 return emit_copy_query_pool_results(cmdbuf, cs, pool, firstQuery,
731 struct tu_cs *cs = &cmdbuf->cs;
737 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 4);
738 tu_cs_emit_qw(cs, query_available_iova(pool, query));
739 tu_cs_emit_qw(cs, 0x0);
754 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 4);
755 tu_cs_emit_qw(cs, result_iova);
756 tu_cs_emit_qw(cs, 0x0);
830 struct tu_cs *cs = cmdbuf->state.pass ? &cmdbuf->draw_cs : &cmdbuf->cs;
834 tu_cs_emit_regs(cs,
837 tu_cs_emit_regs(cs,
840 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
841 tu_cs_emit(cs, ZPASS_DONE);
849 struct tu_cs *cs = cmdbuf->state.pass ? &cmdbuf->draw_cs : &cmdbuf->cs;
860 tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
865 tu6_emit_event_write(cmdbuf, cs, START_PRIMITIVE_CTRS);
867 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
868 tu_cs_emit_qw(cs, global_iova(cmdbuf, vtx_stats_query_not_running));
869 tu_cs_emit(cs, 0);
872 tu_cond_exec_end(cs);
877 tu6_emit_event_write(cmdbuf, cs, START_FRAGMENT_CTRS);
881 tu6_emit_event_write(cmdbuf, cs, START_COMPUTE_CTRS);
884 tu_cs_emit_wfi(cs);
886 tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
887 tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_RBBM_PRIMCTR_0_LO) |
890 tu_cs_emit_qw(cs, begin_iova);
894 emit_perfcntrs_pass_start(struct tu_cs *cs, uint32_t pass)
896 tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
897 tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(
901 tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
909 struct tu_cs *cs = cmdbuf->state.pass ? &cmdbuf->draw_cs : &cmdbuf->cs;
925 * 2) Pick the right cs setting proper pass index to the reg and prepend
932 tu_cs_emit_wfi(cs);
941 tu_cond_exec_end(cs);
942 emit_perfcntrs_pass_start(cs, data->pass);
950 tu_cs_emit_pkt4(cs, counter->select_reg, 1);
951 tu_cs_emit(cs, countable->selector);
953 tu_cond_exec_end(cs);
956 tu_cs_emit_wfi(cs);
965 tu_cond_exec_end(cs);
966 emit_perfcntrs_pass_start(cs, data->pass);
974 tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
975 tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(counter->counter_reg_lo) |
977 tu_cs_emit_qw(cs, begin_iova);
979 tu_cond_exec_end(cs);
988 struct tu_cs *cs = cmdbuf->state.pass ? &cmdbuf->draw_cs : &cmdbuf->cs;
991 tu_cs_emit_regs(cs, A6XX_VPC_SO_STREAM_COUNTS(.qword = begin_iova));
992 tu6_emit_event_write(cmdbuf, cs, WRITE_PRIMITIVE_COUNTS);
1000 struct tu_cs *cs = cmdbuf->state.pass ? &cmdbuf->draw_cs : &cmdbuf->cs;
1015 tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
1020 tu6_emit_event_write(cmdbuf, cs, START_PRIMITIVE_CTRS);
1022 tu_cs_emit_wfi(cs);
1024 tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
1025 tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_RBBM_PRIMCTR_7_LO) |
1028 tu_cs_emit_qw(cs, begin_iova);
1031 tu_cond_exec_end(cs);
1115 struct tu_cs *cs = pass ? &cmdbuf->draw_cs : &cmdbuf->cs;
1121 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 4);
1122 tu_cs_emit_qw(cs, end_iova);
1123 tu_cs_emit_qw(cs, 0xffffffffffffffffull);
1125 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
1127 tu_cs_emit_regs(cs,
1130 tu_cs_emit_regs(cs,
1133 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1134 tu_cs_emit(cs, ZPASS_DONE);
1136 tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
1137 tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_NE) |
1139 tu_cs_emit_qw(cs, end_iova);
1140 tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(0xffffffff));
1141 tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0));
1142 tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
1145 tu_cs_emit_pkt7(cs, CP_MEM_TO_MEM, 9);
1146 tu_cs_emit(cs, CP_MEM_TO_MEM_0_DOUBLE | CP_MEM_TO_MEM_0_NEG_C);
1147 tu_cs_emit_qw(cs, result_iova);
1148 tu_cs_emit_qw(cs, result_iova);
1149 tu_cs_emit_qw(cs, end_iova);
1150 tu_cs_emit_qw(cs, begin_iova);
1152 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
1161 cs = &cmdbuf->draw_epilogue_cs;
1163 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 4);
1164 tu_cs_emit_qw(cs, available_iova);
1165 tu_cs_emit_qw(cs, 0x1);
1180 struct tu_cs *cs,
1192 tu6_emit_event_write(cmdbuf, cs, STOP_PRIMITIVE_CTRS);
1194 tu_cs_reserve(cs, 7 + 2);
1198 tu_cs_emit_pkt7(cs, CP_COND_EXEC, 6);
1199 tu_cs_emit_qw(cs, global_iova(cmdbuf, vtx_stats_query_not_running));
1200 tu_cs_emit_qw(cs, global_iova(cmdbuf, vtx_stats_query_not_running));
1201 tu_cs_emit(cs, CP_COND_EXEC_4_REF(0x2));
1202 tu_cs_emit(cs, 2); /* Cond execute the next 2 DWORDS */
1204 tu6_emit_event_write(cmdbuf, cs, STOP_PRIMITIVE_CTRS);
1209 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
1210 tu_cs_emit_qw(cs, global_iova(cmdbuf, vtx_stats_query_not_running));
1211 tu_cs_emit(cs, 1);
1220 struct tu_cs *cs = cmdbuf->state.pass ? &cmdbuf->draw_cs : &cmdbuf->cs;
1232 emit_stop_primitive_ctrs(cmdbuf, cs, VK_QUERY_TYPE_PIPELINE_STATISTICS);
1236 tu6_emit_event_write(cmdbuf, cs, STOP_FRAGMENT_CTRS);
1240 tu6_emit_event_write(cmdbuf, cs, STOP_COMPUTE_CTRS);
1243 tu_cs_emit_wfi(cs);
1245 tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
1246 tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_RBBM_PRIMCTR_0_LO) |
1249 tu_cs_emit_qw(cs, end_iova);
1256 tu_cs_emit_pkt7(cs, CP_MEM_TO_MEM, 9);
1257 tu_cs_emit(cs, CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES |
1261 tu_cs_emit_qw(cs, result_iova);
1262 tu_cs_emit_qw(cs, result_iova);
1263 tu_cs_emit_qw(cs, stat_stop_iova);
1264 tu_cs_emit_qw(cs, stat_start_iova);
1267 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
1270 cs = &cmdbuf->draw_epilogue_cs;
1273 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 4);
1274 tu_cs_emit_qw(cs, available_iova);
1275 tu_cs_emit_qw(cs, 0x1);
1283 struct tu_cs *cs = cmdbuf->state.pass ? &cmdbuf->draw_cs : &cmdbuf->cs;
1297 tu_cond_exec_end(cs);
1298 emit_perfcntrs_pass_start(cs, data->pass);
1306 tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
1307 tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(counter->counter_reg_lo) |
1309 tu_cs_emit_qw(cs, end_iova);
1311 tu_cond_exec_end(cs);
1314 tu_cs_emit_wfi(cs);
1324 tu_cond_exec_end(cs);
1325 emit_perfcntrs_pass_start(cs, data->pass);
1334 tu_cs_emit_pkt7(cs, CP_MEM_TO_MEM, 9);
1335 tu_cs_emit(cs, CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES |
1339 tu_cs_emit_qw(cs, result_iova);
1340 tu_cs_emit_qw(cs, result_iova);
1341 tu_cs_emit_qw(cs, end_iova);
1342 tu_cs_emit_qw(cs, begin_iova);
1344 tu_cond_exec_end(cs);
1346 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
1349 cs = &cmdbuf->draw_epilogue_cs;
1352 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 4);
1353 tu_cs_emit_qw(cs, available_iova);
1354 tu_cs_emit_qw(cs, 0x1);
1363 struct tu_cs *cs = cmdbuf->state.pass ? &cmdbuf->draw_cs : &cmdbuf->cs;
1374 tu_cs_emit_regs(cs, A6XX_VPC_SO_STREAM_COUNTS(.qword = end_iova));
1375 tu6_emit_event_write(cmdbuf, cs, WRITE_PRIMITIVE_COUNTS);
1377 tu_cs_emit_wfi(cs);
1378 tu6_emit_event_write(cmdbuf, cs, CACHE_FLUSH_TS);
1381 tu_cs_emit_pkt7(cs, CP_MEM_TO_MEM, 9);
1382 tu_cs_emit(cs, CP_MEM_TO_MEM_0_DOUBLE | CP_MEM_TO_MEM_0_NEG_C |
1384 tu_cs_emit_qw(cs, result_written_iova);
1385 tu_cs_emit_qw(cs, result_written_iova);
1386 tu_cs_emit_qw(cs, end_written_iova);
1387 tu_cs_emit_qw(cs, begin_written_iova);
1389 tu6_emit_event_write(cmdbuf, cs, CACHE_FLUSH_TS);
1392 tu_cs_emit_pkt7(cs, CP_MEM_TO_MEM, 9);
1393 tu_cs_emit(cs, CP_MEM_TO_MEM_0_DOUBLE | CP_MEM_TO_MEM_0_NEG_C |
1395 tu_cs_emit_qw(cs, result_generated_iova);
1396 tu_cs_emit_qw(cs, result_generated_iova);
1397 tu_cs_emit_qw(cs, end_generated_iova);
1398 tu_cs_emit_qw(cs, begin_generated_iova);
1401 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 4);
1402 tu_cs_emit_qw(cs, available_iova);
1403 tu_cs_emit_qw(cs, 0x1);
1411 struct tu_cs *cs = cmdbuf->state.pass ? &cmdbuf->draw_cs : &cmdbuf->cs;
1423 tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
1428 tu_cs_emit_wfi(cs);
1430 tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
1431 tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_RBBM_PRIMCTR_7_LO) |
1434 tu_cs_emit_qw(cs, end_iova);
1436 tu_cs_emit_pkt7(cs, CP_MEM_TO_MEM, 9);
1437 tu_cs_emit(cs, CP_MEM_TO_MEM_0_DOUBLE | CP_MEM_TO_MEM_0_NEG_C |
1439 tu_cs_emit_qw(cs, result_iova);
1440 tu_cs_emit_qw(cs, result_iova);
1441 tu_cs_emit_qw(cs, end_iova);
1442 tu_cs_emit_qw(cs, begin_iova);
1444 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
1449 emit_stop_primitive_ctrs(cmdbuf, cs, VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT);
1452 tu_cond_exec_end(cs);
1456 cs = &cmdbuf->draw_epilogue_cs;
1459 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 4);
1460 tu_cs_emit_qw(cs, available_iova);
1461 tu_cs_emit_qw(cs, 0x1);
1493 struct tu_cs *cs = &cmd->draw_epilogue_cs;
1496 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 4);
1497 tu_cs_emit_qw(cs, query_available_iova(pool, query + i));
1498 tu_cs_emit_qw(cs, 0x1);
1572 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs;
1591 tu_cs_emit_wfi(cs);
1594 tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
1595 tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_CP_ALWAYS_ON_COUNTER) |
1598 tu_cs_emit_qw(cs, query_result_iova(pool, query, uint64_t, 0));
1603 cs = cmd->state.pass ? &cmd->draw_epilogue_cs : &cmd->cs;
1605 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 4);
1606 tu_cs_emit_qw(cs, query_available_iova(pool, query));
1607 tu_cs_emit_qw(cs, 0x1);