Lines Matching refs:cs
22 struct tu_cs *cs,
39 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
40 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
42 tu_cs_emit_qw(cs, global_iova(cmd, seqno_dummy));
43 tu_cs_emit(cs, 0);
58 tu_cs_emit_regs(&cmd->cs, A6XX_PC_TESSFACTOR_ADDR(.qword = cmd->device->tess_bo->iova));
66 struct tu_cs *cs,
84 tu6_emit_event_write(cmd_buffer, cs, PC_CCU_FLUSH_COLOR_TS);
87 tu6_emit_event_write(cmd_buffer, cs, PC_CCU_FLUSH_DEPTH_TS);
89 tu6_emit_event_write(cmd_buffer, cs, PC_CCU_INVALIDATE_COLOR);
91 tu6_emit_event_write(cmd_buffer, cs, PC_CCU_INVALIDATE_DEPTH);
93 tu6_emit_event_write(cmd_buffer, cs, CACHE_FLUSH_TS);
95 tu6_emit_event_write(cmd_buffer, cs, CACHE_INVALIDATE);
97 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
101 tu_cs_emit_wfi(cs);
103 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
110 struct tu_cs *cs)
112 tu6_emit_flushes(cmd_buffer, cs, cmd_buffer->state.cache.flush_bits);
120 struct tu_cs *cs)
125 tu6_emit_flushes(cmd_buffer, cs, cmd_buffer->state.renderpass_cache.flush_bits);
136 struct tu_cs *cs,
143 assert(!cs->cond_stack_depth);
169 tu6_emit_flushes(cmd_buffer, cs, flushes);
174 tu_cs_emit_regs(cs,
187 struct tu_cs *cs)
191 tu_cs_emit_regs(cs,
198 tu_cs_emit_regs(cs,
201 tu_cs_emit_regs(cs, A6XX_RB_STENCIL_INFO(0));
211 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
212 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = fmt).value);
214 tu_cs_image_depth_ref(cs, iview, 0);
216 tu_cs_image_ref(cs, &iview->view, 0);
217 tu_cs_emit(cs, tu_attachment_gmem_offset(cmd, attachment));
219 tu_cs_emit_regs(cs,
222 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE, 3);
223 tu_cs_image_flag_ref(cs, &iview->view, 0);
228 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 6);
229 tu_cs_emit(cs, A6XX_RB_STENCIL_INFO(.separate_stencil = true).value);
231 tu_cs_image_stencil_ref(cs, iview, 0);
232 tu_cs_emit(cs, tu_attachment_gmem_offset_stencil(cmd, attachment));
234 tu_cs_image_ref(cs, &iview->view, 0);
235 tu_cs_emit(cs, tu_attachment_gmem_offset(cmd, attachment));
238 tu_cs_emit_regs(cs,
246 struct tu_cs *cs)
265 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
267 tu_cs_emit(cs, 0);
273 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
274 tu_cs_emit(cs, iview->view.RB_MRT_BUF_INFO);
275 tu_cs_image_ref(cs, &iview->view, 0);
276 tu_cs_emit(cs, tu_attachment_gmem_offset(cmd, &cmd->state.pass->attachments[a]));
278 tu_cs_emit_regs(cs,
281 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(i), 3);
282 tu_cs_image_flag_ref(cs, &iview->view, 0);
288 tu_cs_emit_regs(cs, A6XX_GRAS_LRZ_MRT_BUF_INFO_0(.color_format = mrt0_format));
290 tu_cs_emit_regs(cs,
292 tu_cs_emit_regs(cs,
296 tu_cs_emit_regs(cs, A6XX_GRAS_MAX_LAYER_INDEX(layers - 1));
300 tu6_emit_msaa(struct tu_cs *cs, VkSampleCountFlagBits vk_samples,
306 tu_cs_emit_regs(cs,
311 tu_cs_emit_regs(cs,
316 tu_cs_emit_regs(cs,
321 tu_cs_emit_regs(cs,
326 tu6_emit_bin_size(struct tu_cs *cs,
329 tu_cs_emit_regs(cs,
334 tu_cs_emit_regs(cs,
340 tu_cs_emit_regs(cs,
348 struct tu_cs *cs,
381 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CNTL, 1);
382 tu_cs_emit(cs, cntl);
391 tu_cs_reserve(cs, 3 + 4);
392 tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
393 tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
395 tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(4));
398 tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
399 tu_cs_emit(cs, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL));
400 tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
401 tu_cs_emit(cs, cntl);
405 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align)
432 tu_cs_emit_regs(cs,
438 tu6_emit_window_scissor(struct tu_cs *cs,
444 tu_cs_emit_regs(cs,
448 tu_cs_emit_regs(cs,
454 tu6_emit_window_offset(struct tu_cs *cs, uint32_t x1, uint32_t y1)
456 tu_cs_emit_regs(cs,
459 tu_cs_emit_regs(cs,
462 tu_cs_emit_regs(cs,
465 tu_cs_emit_regs(cs,
487 tu_cs_emit_draw_state(struct tu_cs *cs, uint32_t id, struct tu_draw_state state)
536 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(state.size) |
540 tu_cs_emit_qw(cs, state.iova);
629 tu6_emit_cond_for_load_stores(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
633 tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
634 tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(REG_A6XX_VSC_STATE_REG(pipe)) |
644 struct tu_cs *cs,
649 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
650 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM));
656 tu6_emit_window_scissor(cs, x1, y1, x2, y2);
657 tu6_emit_window_offset(cs, x1, y1);
662 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
664 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
665 tu_cs_emit(cs, 0x0);
667 tu_cs_emit_pkt7(cs, CP_SET_BIN_DATA5_OFFSET, 4);
668 tu_cs_emit(cs, tiling->pipe_sizes[pipe] |
670 tu_cs_emit(cs, pipe * cmd->vsc_draw_strm_pitch);
671 tu_cs_emit(cs, pipe * 4);
672 tu_cs_emit(cs, pipe * cmd->vsc_prim_strm_pitch);
675 tu6_emit_cond_for_load_stores(cmd, cs, pipe, slot, hw_binning);
677 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
678 tu_cs_emit(cs, !hw_binning);
680 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
681 tu_cs_emit(cs, 0x0);
686 struct tu_cs *cs,
695 tu_resolve_sysmem(cmd, cs, src, dst, layer_mask, fb->layers, &cmd->state.render_area);
700 struct tu_cs *cs,
725 tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS);
727 tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS);
729 tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE);
732 tu_cs_emit_wfi(cs);
741 tu6_emit_sysmem_resolve(cmd, cs, subpass->multiview_mask, a, gmem_a);
747 tu6_emit_tile_load(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
749 tu6_emit_blit_scissor(cmd, cs, true);
752 tu_load_gmem_attachment(cmd, cs, i, cmd->state.tiling->binning, false);
756 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
761 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
762 tu_cs_emit(cs, 0x0);
764 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
765 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE));
767 tu6_emit_blit_scissor(cmd, cs, true);
771 tu_store_gmem_attachment(cmd, cs, a, a, cmd->state.tiling->binning_possible);
779 tu_store_gmem_attachment(cmd, cs, a, gmem_a, false);
786 tu_disable_draw_states(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
788 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
789 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
792 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
793 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
799 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
804 tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE);
806 tu_cs_emit_regs(cs, A6XX_HLSQ_INVALIDATE_CMD(
820 tu_cs_emit_wfi(cs);
825 tu_cs_emit_regs(cs,
828 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
829 tu_cs_emit_write_reg(cs, REG_A6XX_SP_FLOAT_CNTL, 0);
830 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
831 tu_cs_emit_write_reg(cs, REG_A6XX_SP_PERFCTR_ENABLE, 0x3f);
832 tu_cs_emit_write_reg(cs, REG_A6XX_TPL1_UNKNOWN_B605, 0x44);
833 tu_cs_emit_write_reg(cs, REG_A6XX_TPL1_DBG_ECO_CNTL,
835 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
836 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
838 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
839 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_DBG_ECO_CNTL, 0x880);
840 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
841 tu_cs_emit_write_reg(cs, REG_A6XX_SP_CHICKEN_BITS, 0x00000410);
842 tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
843 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
844 tu_cs_emit_regs(cs, A6XX_HLSQ_SHARED_CONSTS(.enable = false));
845 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
846 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
847 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
848 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A9A8, 0);
849 tu_cs_emit_regs(cs, A6XX_SP_MODE_CONTROL(.constant_demotion_enable = true,
854 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
855 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
856 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
858 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
860 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
861 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
862 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
863 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
864 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
865 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
866 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
867 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
869 tu_cs_emit_regs(cs, A6XX_VPC_POINT_COORD_INVERT(false));
870 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
872 tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(true));
874 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
876 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 0);
877 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
878 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
879 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
880 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
881 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
882 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_MODE_CNTL,
885 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
887 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
889 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
891 tu_cs_emit_regs(cs, A6XX_RB_ALPHA_CONTROL()); /* always disable alpha test */
892 tu_cs_emit_regs(cs, A6XX_RB_DITHER_CNTL()); /* always disable dithering */
894 tu_disable_draw_states(cmd, cs);
896 tu_cs_emit_regs(cs,
899 tu_cs_emit_regs(cs,
934 tu_cs_emit_regs(cs,
936 tu_cs_emit_regs(cs,
938 tu_cs_emit_regs(cs,
942 tu_cs_sanity_check(cs);
946 update_vsc_pipe(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
950 tu_cs_emit_regs(cs,
954 tu_cs_emit_regs(cs,
958 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
959 tu_cs_emit_array(cs, tiling->pipe_config, 32);
961 tu_cs_emit_regs(cs,
965 tu_cs_emit_regs(cs,
971 emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
978 tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
979 tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
981 tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i)));
982 tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
983 tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_draw_strm_pitch - VSC_PAD));
984 tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
985 tu_cs_emit_qw(cs, global_iova(cmd, vsc_draw_overflow));
986 tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(cmd->vsc_draw_strm_pitch));
988 tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
989 tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
991 tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i)));
992 tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
993 tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_prim_strm_pitch - VSC_PAD));
994 tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
995 tu_cs_emit_qw(cs, global_iova(cmd, vsc_prim_overflow));
996 tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(cmd->vsc_prim_strm_pitch));
999 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
1003 tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1008 tu6_emit_window_scissor(cs, 0, 0, fb->width - 1, fb->height - 1);
1010 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1011 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
1013 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1014 tu_cs_emit(cs, 0x1);
1016 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1017 tu_cs_emit(cs, 0x1);
1019 tu_cs_emit_wfi(cs);
1021 tu_cs_emit_regs(cs,
1024 update_vsc_pipe(cmd, cs);
1026 tu_cs_emit_regs(cs,
1029 tu_cs_emit_regs(cs,
1032 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1033 tu_cs_emit(cs, UNK_2C);
1035 tu_cs_emit_regs(cs,
1038 tu_cs_emit_regs(cs,
1041 trace_start_binning_ib(&cmd->trace, cs);
1044 tu_cs_emit_call(cs, &cmd->draw_cs);
1046 trace_end_binning_ib(&cmd->trace, cs);
1055 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1056 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1059 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1060 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1062 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1063 tu_cs_emit(cs, UNK_2D);
1073 tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS);
1075 tu_cs_emit_wfi(cs);
1077 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1079 emit_vsc_overflow_test(cmd, cs);
1081 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1082 tu_cs_emit(cs, 0x0);
1084 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1085 tu_cs_emit(cs, 0x0);
1202 struct tu_cs cs;
1203 struct tu_draw_state ds = tu_cs_draw_state(&cmd->sub_cs, &cs, 9);
1205 tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_FRAG, 3);
1206 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
1211 tu_cs_emit_qw(&cs, texture.iova);
1213 tu_cs_emit_regs(&cs, A6XX_SP_FS_TEX_CONST(.qword = texture.iova));
1215 tu_cs_emit_regs(&cs, A6XX_SP_FS_TEX_COUNT(subpass->input_count * 2));
1217 assert(cs.cur == cs.end); /* validate draw state size */
1225 struct tu_cs *cs = &cmd->draw_cs;
1227 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 6);
1228 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM,
1230 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM,
1239 struct tu_cs *cs = &cmd->draw_cs;
1241 tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_GMEM);
1243 tu6_emit_tile_load(cmd, cs);
1245 tu6_emit_blit_scissor(cmd, cs, false);
1248 tu_clear_gmem_attachment(cmd, cs, i, &clear_values[i]);
1250 tu_cond_exec_end(cs);
1252 tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM);
1255 tu_clear_sysmem_attachment(cmd, cs, i, &clear_values[i]);
1257 tu_cond_exec_end(cs);
1261 tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
1266 tu_lrz_sysmem_begin(cmd, cs);
1269 tu6_emit_window_scissor(cs, 0, 0, fb->width - 1, fb->height - 1);
1270 tu6_emit_window_offset(cs, 0, 0);
1272 tu6_emit_bin_size(cs, 0, 0,
1276 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1277 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
1279 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1280 tu_cs_emit(cs, 0x0);
1282 tu_emit_cache_flush_ccu(cmd, cs, TU_CMD_CCU_SYSMEM);
1284 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1285 tu_cs_emit(cs, 0x1);
1287 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1288 tu_cs_emit(cs, 0x0);
1290 tu_autotune_begin_renderpass(cmd, cs, autotune_result);
1292 tu_cs_sanity_check(cs);
1296 tu6_sysmem_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
1299 tu_autotune_end_renderpass(cmd, cs, autotune_result);
1304 tu6_emit_sysmem_resolves(cmd, cs, cmd->state.subpass);
1306 tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
1308 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1309 tu_cs_emit(cs, 0x0);
1311 tu_lrz_sysmem_end(cmd, cs);
1313 tu_cs_sanity_check(cs);
1317 tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
1322 tu_lrz_tiling_begin(cmd, cs);
1324 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1325 tu_cs_emit(cs, 0x0);
1327 tu_emit_cache_flush_ccu(cmd, cs, TU_CMD_CCU_GMEM);
1330 tu6_emit_bin_size(cs, tiling->tile0.width, tiling->tile0.height,
1334 tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, true);
1336 tu6_emit_binning_pass(cmd, cs);
1338 tu6_emit_bin_size(cs, tiling->tile0.width, tiling->tile0.height,
1342 tu_cs_emit_regs(cs,
1345 tu_cs_emit_regs(cs,
1348 tu_cs_emit_regs(cs,
1351 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1352 tu_cs_emit(cs, 0x1);
1354 tu6_emit_bin_size(cs, tiling->tile0.width, tiling->tile0.height,
1362 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_STATE_REG(0), pipe_count);
1364 tu_cs_emit(cs, ~0);
1368 tu_autotune_begin_renderpass(cmd, cs, autotune_result);
1370 tu_cs_sanity_check(cs);
1374 tu6_render_tile(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
1377 tu6_emit_tile_select(cmd, &cmd->cs, tx, ty, pipe, slot);
1379 trace_start_draw_ib_gmem(&cmd->trace, &cmd->cs);
1385 tu6_emit_event_write(cmd, cs, STOP_PRIMITIVE_CTRS);
1387 tu_cs_emit_call(cs, &cmd->draw_cs);
1390 tu6_emit_event_write(cmd, cs, START_PRIMITIVE_CTRS);
1393 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1394 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
1399 tu6_emit_cond_for_load_stores(cmd, cs, pipe, slot, false);
1401 tu_cs_emit_call(cs, &cmd->tile_store_cs);
1404 tu_cs_emit_wfi(cs);
1405 tu_cs_emit_pkt7(&cmd->cs, CP_WAIT_FOR_ME, 0);
1409 cs, tu_copy_timestamp_buffer);
1412 tu_cs_sanity_check(cs);
1414 trace_end_draw_ib_gmem(&cmd->trace, &cmd->cs);
1418 tu6_tile_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
1421 tu_autotune_end_renderpass(cmd, cs, autotune_result);
1423 tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
1425 tu_lrz_tiling_end(cmd, cs);
1427 tu6_emit_event_write(cmd, cs, PC_CCU_RESOLVE_TS);
1429 tu_cs_sanity_check(cs);
1448 tu6_tile_render_begin(cmd, &cmd->cs, autotune_result);
1476 tu6_render_tile(cmd, &cmd->cs, tx1 + tx, ty, pipe, slot);
1483 tu6_tile_render_end(cmd, &cmd->cs, autotune_result);
1485 trace_end_render_pass(&cmd->trace, &cmd->cs, fb, tiling);
1501 tu6_sysmem_render_begin(cmd, &cmd->cs, autotune_result);
1503 trace_start_draw_ib_sysmem(&cmd->trace, &cmd->cs);
1505 tu_cs_emit_call(&cmd->cs, &cmd->draw_cs);
1507 trace_end_draw_ib_sysmem(&cmd->trace, &cmd->cs);
1509 tu6_sysmem_render_end(cmd, &cmd->cs, autotune_result);
1511 trace_end_render_pass(&cmd->trace, &cmd->cs, cmd->state.framebuffer, cmd->state.tiling);
1530 tu_disable_draw_states(cmd_buffer, &cmd_buffer->cs);
1594 tu_cs_init(&cmd_buffer->cs, device, TU_CS_MODE_GROW, 4096);
1612 tu_cs_finish(&cmd_buffer->cs);
1642 tu_cs_reset(&cmd_buffer->cs);
1790 tu_cs_begin(&cmd_buffer->cs);
1811 tu6_init_hw(cmd_buffer, &cmd_buffer->cs);
1882 struct tu_cs cs;
1884 cmd->state.vertex_buffers.iova = tu_cs_draw_state(&cmd->sub_cs, &cs, 4 * MAX_VBS).iova;
1901 tu_cs_emit_regs(&cs,
1910 tu_cs_draw_state(&cmd->sub_cs, &cs, 2 * MAX_VBS).iova;
1913 tu_cs_emit_regs(&cs, A6XX_VFD_FETCH_STRIDE(i, cmd->state.vb[i].stride));
2033 struct tu_cs *cs, state_cs;
2064 cs = &state_cs;
2073 cs = &cmd->cs;
2076 tu_cs_emit_pkt4(cs, sp_bindless_base_reg, 10);
2077 tu_cs_emit_array(cs, (const uint32_t*) addr, 10);
2078 tu_cs_emit_pkt4(cs, hlsq_bindless_base_reg, 10);
2079 tu_cs_emit_array(cs, (const uint32_t*) addr, 10);
2080 tu_cs_emit_regs(cs, A6XX_HLSQ_INVALIDATE_CMD(.dword = hlsq_invalidate_value));
2083 assert(cs->cur == cs->end); /* validate draw state size */
2192 struct tu_cs *cs = &cmd->draw_cs;
2198 tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
2215 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE(idx), 3);
2216 tu_cs_emit_qw(cs, iova);
2217 tu_cs_emit(cs, size + offset);
2222 tu_cond_exec_end(cs);
2233 struct tu_cs *cs = &cmd->draw_cs;
2235 tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
2239 tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(false));
2243 tu_cs_emit_regs(cs, A6XX_VPC_SO_BUFFER_OFFSET(i, cmd->state.streamout_offset[i]));
2255 tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
2256 tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(idx)) |
2259 tu_cs_emit_qw(cs, buf->iova + counter_buffer_offset);
2262 tu_cs_emit_pkt7(cs, CP_REG_RMW, 3);
2263 tu_cs_emit(cs, CP_REG_RMW_0_DST_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(idx)) |
2265 tu_cs_emit(cs, 0xffffffff);
2266 tu_cs_emit(cs, offset);
2270 tu_cond_exec_end(cs);
2281 struct tu_cs *cs = &cmd->draw_cs;
2283 tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
2287 tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(true));
2292 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_FLUSH_BASE(i), 2);
2293 tu_cs_emit_qw(cs, global_iova(cmd, flush_base[i]));
2294 tu6_emit_event_write(cmd, cs, FLUSH_SO_0 + i);
2308 tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
2309 tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
2314 tu_cs_emit_qw(cs, global_iova(cmd, flush_base[idx]));
2317 tu_cs_emit_pkt7(cs, CP_REG_RMW, 3);
2318 tu_cs_emit(cs, CP_REG_RMW_0_DST_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
2320 tu_cs_emit(cs, 0xffffffff);
2321 tu_cs_emit(cs, -offset);
2324 tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
2325 tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
2327 tu_cs_emit_qw(cs, buf->iova + counter_buffer_offset);
2330 tu_cond_exec_end(cs);
2383 tu_emit_cache_flush(cmd_buffer, &cmd_buffer->cs);
2386 tu_cs_end(&cmd_buffer->cs);
2398 struct tu_cs cs;
2401 cmd->state.dynamic_state[id] = tu_cs_draw_state(&cmd->sub_cs, &cs, size);
2407 return cs;
2412 return cs;
2425 tu_cs_emit_state_ib(&cmd->cs, pipeline->program.state);
2435 struct tu_cs *cs = &cmd->draw_cs;
2443 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * (8 + util_bitcount(mask)));
2444 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM_CONFIG, pipeline->program.config_state);
2445 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM, pipeline->program.state);
2446 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM_BINNING, pipeline->program.binning_state);
2447 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VI, pipeline->vi.state);
2448 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VI_BINNING, pipeline->vi.binning_state);
2449 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_RAST, pipeline->rast_state);
2450 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PRIM_MODE_SYSMEM, pipeline->prim_order_state_sysmem);
2451 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PRIM_MODE_GMEM, pipeline->prim_order_state_gmem);
2454 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DYNAMIC + i, pipeline->dynamic_state[i]);
2467 tu_cs_emit_pkt7(cs, CP_SET_SUBDRAW_SIZE, 1);
2468 tu_cs_emit(cs, subdraw_size);
2482 tu6_emit_msaa(cs, cmd->state.subpass->samples, cmd->state.line_mode);
2603 struct tu_cs cs;
2608 cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_SCISSOR, 1 + 2 * cmd->state.max_scissor);
2609 tu6_emit_scissor(&cs, cmd->state.scissor, cmd->state.max_scissor);
2630 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_DEPTH_BIAS, 4);
2632 tu6_emit_depth_bias(&cs, depthBiasConstantFactor, depthBiasClamp, depthBiasSlopeFactor);
2640 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_BLEND_CONSTANTS, 5);
2642 tu_cs_emit_pkt4(&cs, REG_A6XX_RB_BLEND_RED_F32, 4);
2643 tu_cs_emit_array(&cs, (const uint32_t *) blendConstants, 4);
2652 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_DEPTH_BOUNDS, 3);
2654 tu_cs_emit_regs(&cs,
2674 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK, 2);
2678 tu_cs_emit_regs(&cs, A6XX_RB_STENCILMASK(.dword = cmd->state.dynamic_stencil_mask));
2687 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK, 2);
2691 tu_cs_emit_regs(&cs, A6XX_RB_STENCILWRMASK(.dword = cmd->state.dynamic_stencil_wrmask));
2702 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_STENCIL_REFERENCE, 2);
2706 tu_cs_emit_regs(&cs, A6XX_RB_STENCILREF(.dword = cmd->state.dynamic_stencil_ref));
2714 struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS, 9);
2718 tu6_emit_sample_locations(&cs, pSampleLocationsInfo);
3523 tu_emit_cache_flush(cmd, &cmd->cs);
3531 assert(tu_cs_is_empty(&secondary->cs));
3558 tu_cs_add_entries(&cmd->cs, &secondary->cs);
3573 assert(tu_cs_is_empty(&secondary->cs));
3633 tu_cs_add_entries(&cmd->cs, &secondary->cs);
3863 trace_start_render_pass(&cmd->trace, &cmd->cs);
4001 trace_start_render_pass(&cmd->trace, &cmd->cs);
4048 struct tu_cs *cs = &cmd->draw_cs;
4063 tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_GMEM);
4066 tu6_emit_blit_scissor(cmd, cs, true);
4075 tu_store_gmem_attachment(cmd, cs, a, gmem_a, false);
4084 tu_load_gmem_attachment(cmd, cs, a, false, true);
4088 tu_cond_exec_end(cs);
4090 tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM);
4092 tu6_emit_sysmem_resolves(cmd, cs, subpass);
4094 tu_cond_exec_end(cs);
4122 tu6_emit_user_consts(struct tu_cs *cs,
4135 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_units);
4136 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset / 4) |
4141 tu_cs_emit(cs, 0);
4142 tu_cs_emit(cs, 0);
4144 tu_cs_emit(cs, push_constants[i + offset]);
4149 tu6_emit_shared_consts(struct tu_cs *cs,
4162 tu_cs_emit_pkt7(cs, cp_load_state, 3 + num_units);
4163 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
4168 tu_cs_emit(cs, 0);
4169 tu_cs_emit(cs, 0);
4172 tu_cs_emit(cs, push_constants[i + offset]);
4209 struct tu_cs cs;
4210 tu_cs_begin_sub_stream(&cmd->sub_cs, dwords, &cs);
4213 tu6_emit_shared_consts(&cs, pipeline, cmd->push_constants, compute);
4222 tu6_emit_user_consts(&cs, pipeline, MESA_SHADER_COMPUTE, cmd->push_constants);
4225 tu6_emit_user_consts(&cs, pipeline, type, cmd->push_constants);
4229 return tu_cs_end_draw_state(&cmd->sub_cs, &cs);
4291 tu6_build_depth_plane_z_mode(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
4313 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
4314 tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(zmode));
4316 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
4317 tu_cs_emit(cs, A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(zmode));
4321 tu6_emit_blend(struct tu_cs *cs, struct tu_cmd_buffer *cmd)
4331 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
4333 tu_cs_emit(cs, cmd->state.rb_mrt_control[i] |
4337 tu_cs_emit(cs, cmd->state.rb_mrt_blend_control[i]);
4339 tu_cs_emit(cs, 0);
4340 tu_cs_emit(cs, 0);
4348 tu_cs_emit_pkt4(cs, REG_A6XX_SP_BLEND_CNTL, 1);
4349 tu_cs_emit(cs, cmd->state.sp_blend_cntl |
4353 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_CNTL, 1);
4354 tu_cs_emit(cs, cmd->state.rb_blend_cntl |
4361 struct tu_cs *cs,
4387 tu_emit_cache_flush_renderpass(cmd, cs);
4393 tu_cs_emit_regs(cs, A6XX_PC_PRIMITIVE_CNTL_0(
4409 struct tu_cs cs;
4413 tu_cs_draw_state(&cmd->sub_cs, &cs, size);
4414 tu6_emit_lrz(cmd, &cs);
4415 tu6_build_depth_plane_z_mode(cmd, &cs);
4419 struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_RASTERIZER_DISCARD, 4);
4420 tu_cs_emit_regs(&cs, A6XX_PC_RASTER_CNTL(.dword = cmd->state.pc_raster_cntl));
4421 tu_cs_emit_regs(&cs, A6XX_VPC_UNKNOWN_9107(.dword = cmd->state.vpc_unknown_9107));
4425 struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_GRAS_SU_CNTL, 2);
4426 tu_cs_emit_regs(&cs, A6XX_GRAS_SU_CNTL(.dword = cmd->state.gras_su_cntl));
4430 struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_RB_DEPTH_CNTL, 2);
4444 tu_cs_emit_regs(&cs, A6XX_RB_DEPTH_CNTL(.dword = rb_depth_cntl));
4448 struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_RB_STENCIL_CNTL, 2);
4449 tu_cs_emit_regs(&cs, A6XX_RB_STENCIL_CONTROL(.dword = cmd->state.rb_stencil_cntl));
4456 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_VIEWPORT, 8 + 10 * cmd->state.max_viewport);
4457 tu6_emit_viewport(&cs, cmd->state.viewport, cmd->state.max_viewport,
4462 struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_BLEND,
4464 tu6_emit_blend(&cs, cmd);
4478 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * (TU_DRAW_STATE_COUNT - 2));
4480 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM_CONFIG, pipeline->program.config_state);
4481 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM, pipeline->program.state);
4482 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM_BINNING, pipeline->program.binning_state);
4483 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VI, pipeline->vi.state);
4484 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VI_BINNING, pipeline->vi.binning_state);
4485 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_RAST, pipeline->rast_state);
4486 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PRIM_MODE_SYSMEM, pipeline->prim_order_state_sysmem);
4487 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PRIM_MODE_GMEM, pipeline->prim_order_state_gmem);
4488 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_CONST, cmd->state.shader_const);
4489 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DESC_SETS, cmd->state.desc_sets);
4490 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DESC_SETS_LOAD, pipeline->load_state);
4491 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VB, cmd->state.vertex_buffers);
4492 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_PARAMS, cmd->state.vs_params);
4493 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_LRZ_AND_DEPTH_PLANE, cmd->state.lrz_and_depth_plane_state);
4496 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DYNAMIC + i,
4526 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_count);
4529 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_CONST, cmd->state.shader_const);
4531 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DESC_SETS_LOAD, pipeline->load_state);
4533 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VB, cmd->state.vertex_buffers);
4535 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DYNAMIC + TU_DYNAMIC_STATE_VB_STRIDE,
4539 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DYNAMIC + TU_DYNAMIC_STATE_BLEND,
4543 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_PARAMS, cmd->state.vs_params);
4546 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_LRZ_AND_DEPTH_PLANE, cmd->state.lrz_and_depth_plane_state);
4550 tu_cs_sanity_check(cs);
4655 struct tu_cs cs;
4656 VkResult result = tu_cs_begin_sub_stream(&cmd->sub_cs, 3 + (offset ? 8 : 0), &cs);
4662 tu_cs_emit_regs(&cs,
4667 tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3 + 4);
4668 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
4673 tu_cs_emit(&cs, 0);
4674 tu_cs_emit(&cs, 0);
4676 tu_cs_emit(&cs, 0);
4677 tu_cs_emit(&cs, vertex_offset);
4678 tu_cs_emit(&cs, first_instance);
4679 tu_cs_emit(&cs, 0);
4685 struct tu_cs_entry entry = tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
4699 struct tu_cs *cs = &cmd->draw_cs;
4703 tu6_draw_common(cmd, cs, false, vertexCount);
4705 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
4706 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX));
4707 tu_cs_emit(cs, instanceCount);
4708 tu_cs_emit(cs, vertexCount);
4720 struct tu_cs *cs = &cmd->draw_cs;
4724 tu6_draw_common(cmd, cs, true, indexCount);
4726 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
4727 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_DMA));
4728 tu_cs_emit(cs, instanceCount);
4729 tu_cs_emit(cs, indexCount);
4730 tu_cs_emit(cs, firstIndex);
4731 tu_cs_emit_qw(cs, cmd->state.index_va);
4732 tu_cs_emit(cs, cmd->state.max_index_count);
4758 struct tu_cs *cs = &cmd->draw_cs;
4765 tu6_draw_common(cmd, cs, false, 0);
4767 tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 6);
4768 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX));
4769 tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_NORMAL) |
4771 tu_cs_emit(cs, drawCount);
4772 tu_cs_emit_qw(cs, buf->iova + offset);
4773 tu_cs_emit(cs, stride);
4785 struct tu_cs *cs = &cmd->draw_cs;
4792 tu6_draw_common(cmd, cs, true, 0);
4794 tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 9);
4795 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_DMA));
4796 tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDEXED) |
4798 tu_cs_emit(cs, drawCount);
4799 tu_cs_emit_qw(cs, cmd->state.index_va);
4800 tu_cs_emit(cs, cmd->state.max_index_count);
4801 tu_cs_emit_qw(cs, buf->iova + offset);
4802 tu_cs_emit(cs, stride);
4817 struct tu_cs *cs = &cmd->draw_cs;
4828 tu6_draw_common(cmd, cs, false, 0);
4830 tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 8);
4831 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX));
4832 tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDIRECT_COUNT) |
4834 tu_cs_emit(cs, drawCount);
4835 tu_cs_emit_qw(cs, buf->iova + offset);
4836 tu_cs_emit_qw(cs, count_buf->iova + countBufferOffset);
4837 tu_cs_emit(cs, stride);
4852 struct tu_cs *cs = &cmd->draw_cs;
4858 tu6_draw_common(cmd, cs, true, 0);
4860 tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 11);
4861 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_DMA));
4862 tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDIRECT_COUNT_INDEXED) |
4864 tu_cs_emit(cs, drawCount);
4865 tu_cs_emit_qw(cs, cmd->state.index_va);
4866 tu_cs_emit(cs, cmd->state.max_index_count);
4867 tu_cs_emit_qw(cs, buf->iova + offset);
4868 tu_cs_emit_qw(cs, count_buf->iova + countBufferOffset);
4869 tu_cs_emit(cs, stride);
4883 struct tu_cs *cs = &cmd->draw_cs;
4894 tu6_draw_common(cmd, cs, false, 0);
4896 tu_cs_emit_pkt7(cs, CP_DRAW_AUTO, 6);
4897 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_XFB));
4898 tu_cs_emit(cs, instanceCount);
4899 tu_cs_emit_qw(cs, buf->iova + counterBufferOffset);
4900 tu_cs_emit(cs, counterOffset);
4901 tu_cs_emit(cs, vertexStride);
4930 struct tu_cs *cs, struct tu_pipeline *pipeline,
4962 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_consts);
4963 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
4968 tu_cs_emit(cs, 0);
4969 tu_cs_emit(cs, 0);
4972 tu_cs_emit(cs, driver_params[i]);
4974 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
4975 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
4980 tu_cs_emit_qw(cs, info->indirect->iova + info->indirect_offset);
4989 tu_cs_emit_pkt7(cs, CP_MEM_TO_MEM, 5);
4990 tu_cs_emit(cs, 0);
4991 tu_cs_emit_qw(cs, global_iova(cmd, cs_indirect_xyz[i]));
4992 tu_cs_emit_qw(cs, indirect_iova + i * 4);
4995 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
4996 tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE);
4998 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
4999 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
5004 tu_cs_emit_qw(cs, global_iova(cmd, cs_indirect_xyz[0]));
5011 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 7);
5012 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset + (IR3_DP_BASE_GROUP_X / 4)) |
5017 tu_cs_emit_qw(cs, 0);
5018 tu_cs_emit(cs, 0); /* BASE_GROUP_X */
5019 tu_cs_emit(cs, 0); /* BASE_GROUP_Y */
5020 tu_cs_emit(cs, 0); /* BASE_GROUP_Z */
5021 tu_cs_emit(cs, subgroup_size);
5024 tu_cs_emit(cs, 0); /* LOCAL_GROUP_SIZE_X */
5025 tu_cs_emit(cs, 0); /* LOCAL_GROUP_SIZE_Y */
5026 tu_cs_emit(cs, 0); /* LOCAL_GROUP_SIZE_Z */
5027 tu_cs_emit(cs, subgroup_shift);
5040 struct tu_cs *cs = &cmd->cs;
5046 tu_emit_cache_flush(cmd, cs);
5049 tu_cs_emit_state_ib(cs, tu6_emit_consts(cmd, pipeline, true));
5051 tu_emit_compute_driver_params(cmd, cs, pipeline, info);
5054 tu_cs_emit_state_ib(cs, pipeline->load_state);
5058 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
5059 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE));
5063 tu_cs_emit_regs(cs,
5075 tu_cs_emit_regs(cs,
5080 trace_start_compute(&cmd->trace, cs);
5085 tu_cs_emit_pkt7(cs, CP_EXEC_CS_INDIRECT, 4);
5086 tu_cs_emit(cs, 0x00000000);
5087 tu_cs_emit_qw(cs, iova);
5088 tu_cs_emit(cs,
5093 tu_cs_emit_pkt7(cs, CP_EXEC_CS, 4);
5094 tu_cs_emit(cs, 0x00000000);
5095 tu_cs_emit(cs, CP_EXEC_CS_1_NGROUPS_X(info->blocks[0]));
5096 tu_cs_emit(cs, CP_EXEC_CS_2_NGROUPS_Y(info->blocks[1]));
5097 tu_cs_emit(cs, CP_EXEC_CS_3_NGROUPS_Z(info->blocks[2]));
5100 trace_end_compute(&cmd->trace, cs,
5105 tu_cs_emit_wfi(cs);
5340 struct tu_cs *cs = &cmd->cs;
5345 tu_emit_cache_flush(cmd, cs);
5355 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
5356 tu_cs_emit_qw(cs, event->bo->iova); /* ADDR_LO/HI */
5357 tu_cs_emit(cs, value);
5360 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 4);
5361 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(RB_DONE_TS));
5362 tu_cs_emit_qw(cs, event->bo->iova);
5363 tu_cs_emit(cs, value);
5404 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs;
5409 tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
5410 tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
5412 tu_cs_emit_qw(cs, event->bo->iova); /* POLL_ADDR_LO/HI */
5413 tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(1));
5414 tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0u));
5415 tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
5436 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs;
5438 tu_cs_emit_pkt7(cs, CP_DRAW_PRED_ENABLE_GLOBAL, 1);
5439 tu_cs_emit(cs, 1);
5443 tu_emit_cache_flush_renderpass(cmd, cs);
5445 tu_emit_cache_flush(cmd, cs);
5455 tu_cs_emit_pkt7(cs, CP_MEM_TO_MEM, 5);
5456 tu_cs_emit(cs, 0);
5457 tu_cs_emit_qw(cs, global_iova(cmd, predicate));
5458 tu_cs_emit_qw(cs, iova);
5460 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
5461 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
5464 tu_cs_emit_pkt7(cs, CP_DRAW_PRED_SET, 3);
5465 tu_cs_emit(cs, CP_DRAW_PRED_SET_0_SRC(PRED_SRC_MEM) |
5467 tu_cs_emit_qw(cs, global_iova(cmd, predicate));
5477 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs;
5479 tu_cs_emit_pkt7(cs, CP_DRAW_PRED_ENABLE_GLOBAL, 1);
5480 tu_cs_emit(cs, 0);
5496 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs;
5533 tu_emit_cache_flush_renderpass(cmd, cs);
5535 tu_emit_cache_flush(cmd, cs);
5539 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
5540 tu_cs_emit_qw(cs, va); /* ADDR_LO/HI */
5541 tu_cs_emit(cs, marker);
5544 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 4);
5545 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(RB_DONE_TS));
5546 tu_cs_emit_qw(cs, va);
5547 tu_cs_emit(cs, marker);