Lines Matching refs:cs
37 struct radeon_cmdbuf *cs, unsigned raster_config,
50 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
54 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
57 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
62 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
66 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
71 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
75 si_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs)
79 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
80 radeon_emit(cs, 0);
81 radeon_emit(cs, 0);
82 radeon_emit(cs, 0);
84 radeon_set_sh_reg(cs, R_00B834_COMPUTE_PGM_HI,
87 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
90 radeon_emit(cs, S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en));
91 radeon_emit(cs, S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en));
95 radeon_set_sh_reg_seq(cs, R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
96 radeon_emit(cs, S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en));
97 radeon_emit(cs, S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en));
102 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
103 radeon_emit(cs, bc_va >> 8);
104 radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40));
110 radeon_set_uconfig_reg(cs, R_0301EC_CP_COHER_START_DELAY,
115 radeon_set_sh_reg_seq(cs, R_00B890_COMPUTE_USER_ACCUM_0, 5);
116 radeon_emit(cs, 0); /* R_00B890_COMPUTE_USER_ACCUM_0 */
117 radeon_emit(cs, 0); /* R_00B894_COMPUTE_USER_ACCUM_1 */
118 radeon_emit(cs, 0); /* R_00B898_COMPUTE_USER_ACCUM_2 */
119 radeon_emit(cs, 0); /* R_00B89C_COMPUTE_USER_ACCUM_3 */
120 radeon_emit(cs, 0); /* R_00B8A0_COMPUTE_PGM_RSRC3 */
132 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID, 0x190 /* Default value */);
136 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8);
148 radeon_set_sh_reg_seq(cs, R_00B838_COMPUTE_TBA_LO, 4);
149 radeon_emit(cs, tba_va >> 8);
150 radeon_emit(cs, tba_va >> 40);
151 radeon_emit(cs, tma_va >> 8);
152 radeon_emit(cs, tma_va >> 40);
158 radeon_set_sh_reg_seq(cs, R_00B8AC_COMPUTE_STATIC_THREAD_MGMT_SE4, 4);
159 radeon_emit(cs, S_00B8AC_SA0_CU_EN(spi_cu_en) | S_00B8AC_SA1_CU_EN(spi_cu_en)); /* SE4 */
160 radeon_emit(cs, S_00B8AC_SA0_CU_EN(spi_cu_en) | S_00B8AC_SA1_CU_EN(spi_cu_en)); /* SE5 */
161 radeon_emit(cs, S_00B8AC_SA0_CU_EN(spi_cu_en) | S_00B8AC_SA1_CU_EN(spi_cu_en)); /* SE6 */
162 radeon_emit(cs, S_00B8AC_SA0_CU_EN(spi_cu_en) | S_00B8AC_SA1_CU_EN(spi_cu_en)); /* SE7 */
164 radeon_set_sh_reg(cs, R_00B8BC_COMPUTE_DISPATCH_INTERLEAVE, 64);
176 si_set_raster_config(struct radv_physical_device *physical_device, struct radeon_cmdbuf *cs)
188 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config);
190 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
192 si_write_harvested_raster_configs(physical_device, cs, raster_config, raster_config_1);
197 si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
204 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
205 radeon_emit(cs, CC0_UPDATE_LOAD_ENABLES(1));
206 radeon_emit(cs, CC1_UPDATE_SHADOW_ENABLES(1));
209 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
210 radeon_emit(cs, 0);
214 si_set_raster_config(physical_device, cs);
216 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
218 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
222 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
223 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
228 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
229 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
231 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
235 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
237 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
239 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE,
243 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
249 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
250 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
252 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
255 cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
257 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
259 cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
265 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i * 8, 0);
266 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i * 8, fui(1.0));
271 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
272 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
274 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
275 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
276 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
277 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
278 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
281 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
286 radeon_set_context_reg(cs, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0);
287 radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0);
288 radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0);
289 radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0);
290 radeon_set_uconfig_reg(cs, R_03097C_GE_STEREO_CNTL, 0);
291 radeon_set_uconfig_reg(cs, R_030988_GE_USER_VGPR_EN, 0);
295 cs, R_028038_DB_DFSM_CONTROL,
299 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
300 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
301 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
303 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
312 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
313 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
314 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
318 radeon_set_sh_reg(cs, R_00B524_SPI_SHADER_PGM_HI_LS,
320 radeon_set_sh_reg(cs, R_00B324_SPI_SHADER_PGM_HI_ES,
323 radeon_set_sh_reg(cs, R_00B414_SPI_SHADER_PGM_HI_LS,
325 radeon_set_sh_reg(cs, R_00B214_SPI_SHADER_PGM_HI_ES,
328 radeon_set_sh_reg(cs, R_00B524_SPI_SHADER_PGM_HI_LS,
330 radeon_set_sh_reg(cs, R_00B324_SPI_SHADER_PGM_HI_ES,
335 radeon_set_sh_reg(cs, R_00B124_SPI_SHADER_PGM_HI_VS,
355 ac_set_reg_cu_en(cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS, S_00B404_CU_EN(0xffff),
358 ac_set_reg_cu_en(cs, R_00B104_SPI_SHADER_PGM_RSRC4_VS, S_00B104_CU_EN(0xffff),
361 ac_set_reg_cu_en(cs, R_00B004_SPI_SHADER_PGM_RSRC4_PS, S_00B004_CU_EN(cu_mask_ps >> 16),
367 ac_set_reg_cu_en(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
372 radeon_set_sh_reg_idx(physical_device, cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 3,
375 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
377 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_WAVE_LIMIT(0x3F));
378 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
384 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
389 ac_set_reg_cu_en(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
395 radeon_set_sh_reg_idx(physical_device, cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, 3,
411 radeon_set_context_reg(cs, R_028C50_PA_SC_NGG_MODE_CNTL,
415 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
422 radeon_set_context_reg(cs, R_028838_PA_CL_NGG_CNTL,
442 cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,
463 radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
465 radeon_set_context_reg(cs, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
467 radeon_set_sh_reg_seq(cs, R_00B0C8_SPI_SHADER_USER_ACCUM_PS_0, 4);
468 radeon_emit(cs, 0); /* R_00B0C8_SPI_SHADER_USER_ACCUM_PS_0 */
469 radeon_emit(cs, 0); /* R_00B0CC_SPI_SHADER_USER_ACCUM_PS_1 */
470 radeon_emit(cs, 0); /* R_00B0D0_SPI_SHADER_USER_ACCUM_PS_2 */
471 radeon_emit(cs, 0); /* R_00B0D4_SPI_SHADER_USER_ACCUM_PS_3 */
474 radeon_set_sh_reg_seq(cs, R_00B1C8_SPI_SHADER_USER_ACCUM_VS_0, 4);
475 radeon_emit(cs, 0); /* R_00B1C8_SPI_SHADER_USER_ACCUM_VS_0 */
476 radeon_emit(cs, 0); /* R_00B1CC_SPI_SHADER_USER_ACCUM_VS_1 */
477 radeon_emit(cs, 0); /* R_00B1D0_SPI_SHADER_USER_ACCUM_VS_2 */
478 radeon_emit(cs, 0); /* R_00B1D4_SPI_SHADER_USER_ACCUM_VS_3 */
481 radeon_set_sh_reg_seq(cs, R_00B2C8_SPI_SHADER_USER_ACCUM_ESGS_0, 4);
482 radeon_emit(cs, 0); /* R_00B2C8_SPI_SHADER_USER_ACCUM_ESGS_0 */
483 radeon_emit(cs, 0); /* R_00B2CC_SPI_SHADER_USER_ACCUM_ESGS_1 */
484 radeon_emit(cs, 0); /* R_00B2D0_SPI_SHADER_USER_ACCUM_ESGS_2 */
485 radeon_emit(cs, 0); /* R_00B2D4_SPI_SHADER_USER_ACCUM_ESGS_3 */
486 radeon_set_sh_reg_seq(cs, R_00B4C8_SPI_SHADER_USER_ACCUM_LSHS_0, 4);
487 radeon_emit(cs, 0); /* R_00B4C8_SPI_SHADER_USER_ACCUM_LSHS_0 */
488 radeon_emit(cs, 0); /* R_00B4CC_SPI_SHADER_USER_ACCUM_LSHS_1 */
489 radeon_emit(cs, 0); /* R_00B4D0_SPI_SHADER_USER_ACCUM_LSHS_2 */
490 radeon_emit(cs, 0); /* R_00B4D4_SPI_SHADER_USER_ACCUM_LSHS_3 */
492 radeon_set_sh_reg(cs, R_00B0C0_SPI_SHADER_REQ_CTRL_PS,
496 radeon_set_sh_reg(cs, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
499 radeon_set_context_reg(cs, R_028750_SX_PS_DOWNCONVERT_CONTROL, 0xff);
502 cs, R_028848_PA_CL_VRS_CNTL,
508 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
522 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
524 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
525 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
531 radeon_set_context_reg(cs, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
533 radeon_set_context_reg(cs, R_028084_TA_BC_BASE_ADDR_HI,
540 cs, R_028C48_PA_SC_BINNER_CNTL_1,
543 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
545 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
549 radeon_set_context_reg(cs, R_028A00_PA_SU_POINT_SIZE,
551 radeon_set_context_reg(cs, R_028A04_PA_SU_POINT_MINMAX,
556 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL, S_028004_ZPASS_INCREMENT_DISABLE(1));
570 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL, small_prim_filter_cntl);
574 cs, R_0286D4_SPI_INTERP_CONTROL_0,
582 radeon_set_context_reg(cs, R_028BE4_PA_SU_VTX_CNTL,
586 radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL,
605 radeon_set_sh_reg_seq(cs, regs[i], 4);
606 radeon_emit(cs, tba_va >> 8);
607 radeon_emit(cs, tba_va >> 40);
608 radeon_emit(cs, tma_va >> 8);
609 radeon_emit(cs, tma_va >> 40);
616 radeon_set_context_reg(cs, R_028BDC_PA_SC_LINE_CNTL, 0);
619 radeon_set_context_reg(cs, R_028C54_PA_SC_BINNER_CNTL_2, 0);
620 radeon_set_context_reg(cs, R_028620_PA_RATE_CNTL,
623 radeon_set_uconfig_reg(cs, R_031110_SPI_GS_THROTTLE_CNTL1, 0x12355123);
624 radeon_set_uconfig_reg(cs, R_031114_SPI_GS_THROTTLE_CNTL2, 0x1544D);
627 si_emit_compute(device, cs);
633 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, AMD_IP_GFX);
634 if (!cs)
637 si_emit_graphics(device, cs);
639 while (cs->cdw & 7) {
641 radeon_emit(cs, PKT2_NOP_PAD);
643 radeon_emit(cs, PKT3_NOP_PAD);
647 device->ws->buffer_create(device->ws, cs->cdw * 4, 4096, device->ws->cs_domain(device->ws),
660 memcpy(map, cs->buf, cs->cdw * 4);
663 device->gfx_init_size_dw = cs->cdw;
665 device->ws->cs_destroy(cs);
717 si_write_scissors(struct radeon_cmdbuf *cs, int first, int count, const VkRect2D *scissors,
727 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
744 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) | S_028250_TL_Y(scissor.offset.y) |
746 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
770 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
771 radeon_emit(cs, fui(guardband_y));
772 radeon_emit(cs, fui(discard_y));
773 radeon_emit(cs, fui(guardband_x));
774 radeon_emit(cs, fui(discard_x));
927 si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, bool is_mec,
949 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
950 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
951 radeon_emit(cs, gfx9_eop_bug_va);
952 radeon_emit(cs, gfx9_eop_bug_va >> 32);
955 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false));
956 radeon_emit(cs, op);
957 radeon_emit(cs, sel);
958 radeon_emit(cs, va); /* address lo */
959 radeon_emit(cs, va >> 32); /* address hi */
960 radeon_emit(cs, new_fence); /* immediate data lo */
961 radeon_emit(cs, 0); /* immediate data hi */
963 radeon_emit(cs, 0); /* unused */
975 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 5, false));
976 radeon_emit(cs, op);
977 radeon_emit(cs, sel);
978 radeon_emit(cs, va); /* address lo */
979 radeon_emit(cs, va >> 32); /* address hi */
980 radeon_emit(cs, new_fence); /* immediate data lo */
981 radeon_emit(cs, 0); /* immediate data hi */
983 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, false));
984 radeon_emit(cs, op);
985 radeon_emit(cs, va);
986 radeon_emit(cs, ((va >> 32) & 0xffff) | EOS_DATA_SEL(EOS_DATA_SEL_VALUE_32BIT));
987 radeon_emit(cs, new_fence);
995 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
996 radeon_emit(cs, op);
997 radeon_emit(cs, va);
998 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
999 radeon_emit(cs, 0); /* immediate data */
1000 radeon_emit(cs, 0); /* unused */
1003 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
1004 radeon_emit(cs, op);
1005 radeon_emit(cs, va);
1006 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
1007 radeon_emit(cs, new_fence); /* immediate data */
1008 radeon_emit(cs, 0); /* unused */
1014 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va, uint32_t ref, uint32_t mask)
1019 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
1020 radeon_emit(cs, op | WAIT_REG_MEM_MEM_SPACE(1));
1021 radeon_emit(cs, va);
1022 radeon_emit(cs, va >> 32);
1023 radeon_emit(cs, ref); /* reference value */
1024 radeon_emit(cs, mask); /* mask */
1025 radeon_emit(cs, 4); /* poll interval */
1029 si_emit_acquire_mem(struct radeon_cmdbuf *cs, bool is_mec, bool is_gfx9, unsigned cp_coher_cntl)
1033 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) | PKT3_SHADER_TYPE_S(is_mec));
1034 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
1035 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1036 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
1037 radeon_emit(cs, 0); /* CP_COHER_BASE */
1038 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1039 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1042 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false));
1043 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
1044 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1045 radeon_emit(cs, 0); /* CP_COHER_BASE */
1046 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1051 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level,
1100 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1101 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1109 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1110 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1135 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1136 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1140 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1141 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1148 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1149 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
1182 cs, gfx_level, false, cb_db_event,
1188 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va, *flush_cnt, 0xffffffff);
1193 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1194 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1203 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1204 radeon_emit(cs, 0); /* CP_COHER_CNTL */
1205 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1206 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1207 radeon_emit(cs, 0); /* CP_COHER_BASE */
1208 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1209 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1210 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1216 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1217 radeon_emit(cs, 0);
1223 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1224 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) | EVENT_INDEX(0));
1226 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1227 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | EVENT_INDEX(0));
1232 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, uint32_t *flush_cnt,
1242 gfx10_cs_emit_cache_flush(cs, gfx_level, flush_cnt, flush_va, is_mec, flush_bits,
1266 si_cs_emit_write_event_eop(cs, gfx_level, is_mec, V_028A90_FLUSH_AND_INV_CB_DATA_TS, 0,
1281 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1282 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1288 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1289 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1295 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1296 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1300 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1301 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1307 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1308 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1350 si_cs_emit_write_event_eop(cs, gfx_level, false, cb_db_event, tc_flags, EOP_DST_SEL_MEM,
1352 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va, *flush_cnt, 0xffffffff);
1357 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1358 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1363 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1364 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1373 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1374 radeon_emit(cs, 0);
1381 si_emit_acquire_mem(cs, is_mec, gfx_level == GFX9,
1396 cs, is_mec, gfx_level == GFX9,
1403 si_emit_acquire_mem(cs, is_mec, gfx_level == GFX9,
1415 si_emit_acquire_mem(cs, is_mec, gfx_level == GFX9, cp_coher_cntl);
1418 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1419 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) | EVENT_INDEX(0));
1421 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1422 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | EVENT_INDEX(0));
1444 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1446 si_cs_emit_cache_flush(cmd_buffer->cs, cmd_buffer->device->physical_device->rad_info.gfx_level,
1491 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1492 radeon_emit(cmd_buffer->cs, op);
1493 radeon_emit(cmd_buffer->cs, va);
1494 radeon_emit(cmd_buffer->cs, va >> 32);
1496 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1497 radeon_emit(cmd_buffer->cs, va);
1498 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1532 si_cs_emit_cp_dma(struct radv_device *device, struct radeon_cmdbuf *cs, bool predicating,
1539 radeon_check_space(device->ws, cs, 9);
1571 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, predicating));
1572 radeon_emit(cs, header);
1573 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1574 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1575 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1576 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1577 radeon_emit(cs, command);
1581 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, predicating));
1582 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1583 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1584 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1585 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1586 radeon_emit(cs, command);
1594 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1598 si_cs_emit_cp_dma(device, cs, predicating, dst_va, src_va, size, flags);
1607 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1608 radeon_emit(cs, 0);
1620 si_cs_cp_dma_prefetch(const struct radv_device *device, struct radeon_cmdbuf *cs, uint64_t va,
1632 radeon_check_space(ws, cs, 9);
1650 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, predicating));
1651 radeon_emit(cs, header);
1652 radeon_emit(cs, aligned_va); /* SRC_ADDR_LO [31:0] */
1653 radeon_emit(cs, aligned_va >> 32); /* SRC_ADDR_HI [31:0] */
1654 radeon_emit(cs, aligned_va); /* DST_ADDR_LO [31:0] */
1655 radeon_emit(cs, aligned_va >> 32); /* DST_ADDR_HI [31:0] */
1656 radeon_emit(cs, command);
1662 si_cs_cp_dma_prefetch(cmd_buffer->device, cmd_buffer->cs, va, size,
1895 radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples)
1900 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1901 radeon_emit(cs, (uint32_t)centroid_priority_1x);
1902 radeon_emit(cs, centroid_priority_1x >> 32);
1903 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x);
1904 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x);
1905 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x);
1906 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x);
1909 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1910 radeon_emit(cs, (uint32_t)centroid_priority_2x);
1911 radeon_emit(cs, centroid_priority_2x >> 32);
1912 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x);
1913 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x);
1914 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x);
1915 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x);
1918 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1919 radeon_emit(cs, (uint32_t)centroid_priority_4x);
1920 radeon_emit(cs, centroid_priority_4x >> 32);
1921 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x);
1922 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x);
1923 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x);
1924 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x);
1927 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1928 radeon_emit(cs, (uint32_t)centroid_priority_8x);
1929 radeon_emit(cs, centroid_priority_8x >> 32);
1930 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1931 radeon_emit_array(cs, sample_locs_8x, 4);
1932 radeon_emit_array(cs, sample_locs_8x, 4);
1933 radeon_emit_array(cs, sample_locs_8x, 4);
1934 radeon_emit_array(cs, sample_locs_8x, 2);