Lines Matching refs:cs
64 radv_emit_wait_for_idle(struct radv_device *device, struct radeon_cmdbuf *cs, int family)
68 cs, device->physical_device->rad_info.gfx_level, NULL, 0,
79 radv_emit_thread_trace_start(struct radv_device *device, struct radeon_cmdbuf *cs,
97 cs, R_030800_GRBM_GFX_INDEX,
103 cs, R_008D04_SQ_THREAD_TRACE_BUF0_SIZE,
106 radeon_set_privileged_config_reg(cs, R_008D00_SQ_THREAD_TRACE_BUF0_BASE, shifted_va);
109 cs, R_008D14_SQ_THREAD_TRACE_MASK,
130 radeon_set_privileged_config_reg(cs, R_008D18_SQ_THREAD_TRACE_TOKEN_MASK,
134 radeon_set_privileged_config_reg(cs, R_008D1C_SQ_THREAD_TRACE_CTRL,
138 radeon_set_uconfig_reg(cs, R_030CDC_SQ_THREAD_TRACE_BASE2,
141 radeon_set_uconfig_reg(cs, R_030CC0_SQ_THREAD_TRACE_BASE, shifted_va);
143 radeon_set_uconfig_reg(cs, R_030CC4_SQ_THREAD_TRACE_SIZE, S_030CC4_SIZE(shifted_size));
145 radeon_set_uconfig_reg(cs, R_030CD4_SQ_THREAD_TRACE_CTRL, S_030CD4_RESET_BUFFER(1));
156 radeon_set_uconfig_reg(cs, R_030CC8_SQ_THREAD_TRACE_MASK, thread_trace_mask);
160 cs, R_030CCC_SQ_THREAD_TRACE_TOKEN_MASK,
164 radeon_set_uconfig_reg(cs, R_030CD0_SQ_THREAD_TRACE_PERF_MASK,
167 radeon_set_uconfig_reg(cs, R_030CE0_SQ_THREAD_TRACE_TOKEN_MASK2, 0xffffffff);
169 radeon_set_uconfig_reg(cs, R_030CEC_SQ_THREAD_TRACE_HIWATER, S_030CEC_HIWATER(4));
173 radeon_set_uconfig_reg(cs, R_030CE8_SQ_THREAD_TRACE_STATUS, S_030CE8_UTC_ERROR(0));
188 radeon_set_uconfig_reg(cs, R_030CD8_SQ_THREAD_TRACE_MODE, thread_trace_mode);
193 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
199 radeon_set_sh_reg(cs, R_00B878_COMPUTE_THREAD_TRACE_ENABLE, S_00B878_THREAD_TRACE_ENABLE(1));
201 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
202 radeon_emit(cs, EVENT_TYPE(V_028A90_THREAD_TRACE_START) | EVENT_INDEX(0));
225 radv_copy_thread_trace_info_regs(struct radv_device *device, struct radeon_cmdbuf *cs,
245 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
246 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_PERF) | COPY_DATA_DST_SEL(COPY_DATA_TC_L2) |
248 radeon_emit(cs, thread_trace_info_regs[i] >> 2);
249 radeon_emit(cs, 0); /* unused */
250 radeon_emit(cs, (info_va + i * 4));
251 radeon_emit(cs, (info_va + i * 4) >> 32);
256 radv_emit_thread_trace_stop(struct radv_device *device, struct radeon_cmdbuf *cs,
263 radeon_set_sh_reg(cs, R_00B878_COMPUTE_THREAD_TRACE_ENABLE, S_00B878_THREAD_TRACE_ENABLE(0));
265 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
266 radeon_emit(cs, EVENT_TYPE(V_028A90_THREAD_TRACE_STOP) | EVENT_INDEX(0));
269 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
270 radeon_emit(cs, EVENT_TYPE(V_028A90_THREAD_TRACE_FINISH) | EVENT_INDEX(0));
274 radv_emit_wait_for_idle(device, cs, qf);
283 cs, R_030800_GRBM_GFX_INDEX,
289 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
291 cs,
293 radeon_emit(cs, R_008D20_SQ_THREAD_TRACE_STATUS >> 2); /* register */
294 radeon_emit(cs, 0);
295 radeon_emit(cs, 0); /* reference value */
296 radeon_emit(cs, ~C_008D20_FINISH_DONE);
297 radeon_emit(cs, 4); /* poll interval */
301 radeon_set_privileged_config_reg(cs, R_008D1C_SQ_THREAD_TRACE_CTRL,
305 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
307 cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
308 radeon_emit(cs, R_008D20_SQ_THREAD_TRACE_STATUS >> 2); /* register */
309 radeon_emit(cs, 0);
310 radeon_emit(cs, 0); /* reference value */
311 radeon_emit(cs, ~C_008D20_BUSY); /* mask */
312 radeon_emit(cs, 4); /* poll interval */
315 radeon_set_uconfig_reg(cs, R_030CD8_SQ_THREAD_TRACE_MODE, S_030CD8_MODE(0));
318 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
320 cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
321 radeon_emit(cs, R_030CE8_SQ_THREAD_TRACE_STATUS >> 2); /* register */
322 radeon_emit(cs, 0);
323 radeon_emit(cs, 0); /* reference value */
324 radeon_emit(cs, ~C_030CE8_BUSY); /* mask */
325 radeon_emit(cs, 4); /* poll interval */
328 radv_copy_thread_trace_info_regs(device, cs, se);
332 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
342 struct radeon_cmdbuf *cs = cmd_buffer->cs;
352 radeon_check_space(device->ws, cs, 2 + count);
357 radeon_set_uconfig_reg_seq_perfctr(cs, R_030D08_SQ_THREAD_TRACE_USERDATA_2, count);
359 radeon_set_uconfig_reg_seq(cs, R_030D08_SQ_THREAD_TRACE_USERDATA_2, count);
360 radeon_emit_array(cs, dwords, count);
368 radv_emit_spi_config_cntl(struct radv_device *device, struct radeon_cmdbuf *cs, bool enable)
378 radeon_set_uconfig_reg(cs, R_031100_SPI_CONFIG_CNTL, spi_config_cntl);
382 cs, R_009100_SPI_CONFIG_CNTL,
388 radv_emit_inhibit_clockgating(struct radv_device *device, struct radeon_cmdbuf *cs, bool inhibit)
394 radeon_set_uconfig_reg(cs, R_037390_RLC_PERFMON_CLK_CNTL,
397 radeon_set_uconfig_reg(cs, R_0372FC_RLC_PERFMON_CLK_CNTL,
534 struct radeon_cmdbuf *cs;
543 cs = ws->cs_create(ws, radv_queue_ring(queue));
544 if (!cs)
549 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
550 radeon_emit(cs, CC0_UPDATE_LOAD_ENABLES(1));
551 radeon_emit(cs, CC1_UPDATE_SHADOW_ENABLES(1));
554 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
555 radeon_emit(cs, 0);
563 radv_emit_wait_for_idle(device, cs, family);
566 radv_emit_inhibit_clockgating(device, cs, true);
569 radv_emit_spi_config_cntl(device, cs, true);
571 radv_perfcounter_emit_spm_reset(cs);
575 radv_perfcounter_emit_shaders(cs, 0x7f);
577 radv_emit_spm_setup(device, cs);
581 radv_emit_thread_trace_start(device, cs, family);
584 radv_perfcounter_emit_spm_start(device, cs, family);
586 result = ws->cs_finalize(cs);
588 ws->cs_destroy(cs);
592 device->thread_trace.start_cs[family] = cs;
594 return radv_queue_internal_submit(queue, cs);
603 struct radeon_cmdbuf *cs;
612 cs = ws->cs_create(ws, radv_queue_ring(queue));
613 if (!cs)
618 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
619 radeon_emit(cs, CC0_UPDATE_LOAD_ENABLES(1));
620 radeon_emit(cs, CC1_UPDATE_SHADOW_ENABLES(1));
623 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
624 radeon_emit(cs, 0);
632 radv_emit_wait_for_idle(device, cs, family);
635 radv_perfcounter_emit_spm_stop(device, cs, family);
638 radv_emit_thread_trace_stop(device, cs, family);
640 radv_perfcounter_emit_spm_reset(cs);
643 radv_emit_spi_config_cntl(device, cs, false);
646 radv_emit_inhibit_clockgating(device, cs, false);
648 result = ws->cs_finalize(cs);
650 ws->cs_destroy(cs);
654 device->thread_trace.stop_cs[family] = cs;
656 return radv_queue_internal_submit(queue, cs);