Lines Matching refs:cs
54 struct compiled_stencil_ref *cs = &ctx->stencil_ref;
59 cs->PE_STENCIL_CONFIG[i] =
61 cs->PE_STENCIL_CONFIG_EXT[i] =
135 struct compiled_framebuffer_state *cs = &ctx->framebuffer;
160 cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT_EXT(fmt) |
163 cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT(fmt);
168 cs->PE_COLOR_FORMAT |=
173 cs->PE_COLOR_FORMAT |= COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW);
195 cs->PE_PIPE_COLOR_ADDR[i] = cbuf->reloc[i];
196 cs->PE_PIPE_COLOR_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
199 cs->PE_COLOR_ADDR = cbuf->reloc[0];
200 cs->PE_COLOR_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
203 cs->PE_COLOR_STRIDE = cbuf->surf.stride;
206 cs->TS_COLOR_CLEAR_VALUE = cbuf->level->clear_value;
207 cs->TS_COLOR_CLEAR_VALUE_EXT = cbuf->level->clear_value >> 32;
209 cs->TS_COLOR_STATUS_BASE = cbuf->ts_reloc;
210 cs->TS_COLOR_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
212 cs->TS_COLOR_SURFACE_BASE = cbuf->reloc[0];
213 cs->TS_COLOR_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
220 cs->PE_COLOR_FORMAT &= ~VIVS_PE_COLOR_FORMAT_OVERWRITE;
233 cs->PS_CONTROL = COND(util_format_is_unorm(cbuf->base.format), VIVS_PS_CONTROL_SATURATE_RT0);
234 cs->PS_CONTROL_EXT =
240 cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_OVERWRITE;
241 cs->PE_COLOR_STRIDE = 0;
242 cs->TS_COLOR_STATUS_BASE.bo = NULL;
243 cs->TS_COLOR_SURFACE_BASE.bo = NULL;
245 cs->PE_COLOR_ADDR = screen->dummy_rt_reloc;
247 cs->PE_PIPE_COLOR_ADDR[i] = screen->dummy_rt_reloc;
266 cs->PE_DEPTH_CONFIG =
276 cs->PE_PIPE_DEPTH_ADDR[i] = zsbuf->reloc[i];
277 cs->PE_PIPE_DEPTH_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
280 cs->PE_DEPTH_ADDR = zsbuf->reloc[0];
281 cs->PE_DEPTH_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
284 cs->PE_DEPTH_STRIDE = zsbuf->surf.stride;
285 cs->PE_HDEPTH_CONTROL = VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED;
286 cs->PE_DEPTH_NORMALIZE = fui(exp2f(depth_bits) - 1.0f);
289 cs->TS_DEPTH_CLEAR_VALUE = zsbuf->level->clear_value;
291 cs->TS_DEPTH_STATUS_BASE = zsbuf->ts_reloc;
292 cs->TS_DEPTH_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
294 cs->TS_DEPTH_SURFACE_BASE = zsbuf->reloc[0];
295 cs->TS_DEPTH_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
311 cs->PE_DEPTH_CONFIG = VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE;
312 cs->PE_DEPTH_ADDR.bo = NULL;
313 cs->PE_DEPTH_STRIDE = 0;
314 cs->TS_DEPTH_STATUS_BASE.bo = NULL;
315 cs->TS_DEPTH_SURFACE_BASE.bo = NULL;
318 cs->PE_PIPE_DEPTH_ADDR[i].bo = NULL;
331 cs->GL_MULTI_SAMPLE_CONFIG =
333 cs->msaa_mode = false;
336 cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X;
337 cs->msaa_mode = true; /* Add input to PS */
338 cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
339 cs->RA_MULTISAMPLE_UNK00E10[0] = 0x0000aa22;
340 cs->RA_CENTROID_TABLE[0] = 0x66aa2288;
341 cs->RA_CENTROID_TABLE[1] = 0x88558800;
342 cs->RA_CENTROID_TABLE[2] = 0x88881100;
343 cs->RA_CENTROID_TABLE[3] = 0x33888800;
346 cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X;
347 cs->msaa_mode = true; /* Add input to PS */
348 cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
349 cs->RA_MULTISAMPLE_UNK00E10[0] = 0xeaa26e26;
350 cs->RA_MULTISAMPLE_UNK00E10[1] = 0xe6ae622a;
351 cs->RA_MULTISAMPLE_UNK00E10[2] = 0xaaa22a22;
352 cs->RA_CENTROID_TABLE[0] = 0x4a6e2688;
353 cs->RA_CENTROID_TABLE[1] = 0x888888a2;
354 cs->RA_CENTROID_TABLE[2] = 0x888888ea;
355 cs->RA_CENTROID_TABLE[3] = 0x888888c6;
356 cs->RA_CENTROID_TABLE[4] = 0x46622a88;
357 cs->RA_CENTROID_TABLE[5] = 0x888888ae;
358 cs->RA_CENTROID_TABLE[6] = 0x888888e6;
359 cs->RA_CENTROID_TABLE[7] = 0x888888ca;
360 cs->RA_CENTROID_TABLE[8] = 0x262a2288;
361 cs->RA_CENTROID_TABLE[9] = 0x886688a2;
362 cs->RA_CENTROID_TABLE[10] = 0x888866aa;
363 cs->RA_CENTROID_TABLE[11] = 0x668888a6;
367 cs->TS_MEM_CONFIG = ts_mem_config;
368 cs->PE_MEM_CONFIG = pe_mem_config;
378 cs->PE_LOGIC_OP = pe_logic_op;
409 struct compiled_viewport_state *cs = &ctx->viewport;
425 cs->PA_VIEWPORT_SCALE_X = etna_f32_to_fixp16(vs->scale[0]);
426 cs->PA_VIEWPORT_SCALE_Y = etna_f32_to_fixp16(vs->scale[1]);
427 cs->PA_VIEWPORT_SCALE_Z = fui(vs->scale[2] * 2.0f);
428 cs->PA_VIEWPORT_OFFSET_X = etna_f32_to_fixp16(vs->translate[0]);
429 cs->PA_VIEWPORT_OFFSET_Y = etna_f32_to_fixp16(vs->translate[1]);
430 cs->PA_VIEWPORT_OFFSET_Z = fui(vs->translate[2] - vs->scale[2]);
435 cs->SE_SCISSOR_LEFT = MAX2(vs->translate[0] - fabsf(vs->scale[0]), 0.0f);
436 cs->SE_SCISSOR_TOP = MAX2(vs->translate[1] - fabsf(vs->scale[1]), 0.0f);
437 cs->SE_SCISSOR_RIGHT = ceilf(MAX2(vs->translate[0] + fabsf(vs->scale[0]), 0.0f));
438 cs->SE_SCISSOR_BOTTOM = ceilf(MAX2(vs->translate[1] + fabsf(vs->scale[1]), 0.0f));
440 cs->PE_DEPTH_NEAR = fui(0.0); /* not affected if depth mode is Z (as in GL) */
441 cs->PE_DEPTH_FAR = fui(1.0);
459 struct compiled_set_vertex_buffer *cs = &so->cvb[idx];
466 cs->FE_VERTEX_STREAM_BASE_ADDR.bo = etna_resource(vbi->buffer.resource)->bo;
467 cs->FE_VERTEX_STREAM_BASE_ADDR.offset = vbi->buffer_offset;
468 cs->FE_VERTEX_STREAM_BASE_ADDR.flags = ETNA_RELOC_READ;
469 cs->FE_VERTEX_STREAM_CONTROL =
472 cs->FE_VERTEX_STREAM_BASE_ADDR.bo = NULL;
473 cs->FE_VERTEX_STREAM_CONTROL = 0;
534 struct compiled_vertex_elements_state *cs = CALLOC_STRUCT(compiled_vertex_elements_state);
536 if (!cs)
542 FREE(cs);
549 cs->num_elements = num_elements;
582 cs->FE_VERTEX_ELEMENT_CONFIG[idx] =
591 cs->NFE_GENERIC_ATTRIB_CONFIG0[idx] =
597 cs->NFE_GENERIC_ATTRIB_CONFIG1[idx] =
603 cs->NFE_GENERIC_ATTRIB_SCALE[idx] = 1;
605 cs->NFE_GENERIC_ATTRIB_SCALE[idx] = fui(1.0f);
609 assert(cs->NFE_VERTEX_STREAMS_VERTEX_DIVISOR[buffer_idx] == elements[idx].instance_divisor);
611 cs->NFE_VERTEX_STREAMS_VERTEX_DIVISOR[buffer_idx] = elements[idx].instance_divisor;
614 cs->num_buffers = MAX2(cs->num_buffers, buffer_idx + 1);
617 return cs;