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Searched refs:reg_val (Results 1 - 25 of 658) sorted by relevance

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/kernel/linux/linux-5.10/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_mtl.c23 u32 reg_val; in sxgbe_mtl_init() local
25 reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
26 reg_val &= ETS_RST; in sxgbe_mtl_init()
31 reg_val &= ETS_WRR; in sxgbe_mtl_init()
34 reg_val |= ETS_WFQ; in sxgbe_mtl_init()
37 reg_val |= ETS_DWRR; in sxgbe_mtl_init()
40 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
44 reg_val &= RAA_SP; in sxgbe_mtl_init()
47 reg_val |= RAA_WSP; in sxgbe_mtl_init()
50 writel(reg_val, ioadd in sxgbe_mtl_init()
64 u32 fifo_bits, reg_val; sxgbe_mtl_set_txfifosize() local
76 u32 fifo_bits, reg_val; sxgbe_mtl_set_rxfifosize() local
87 u32 reg_val; sxgbe_mtl_enable_txqueue() local
96 u32 reg_val; sxgbe_mtl_disable_txqueue() local
106 u32 reg_val; sxgbe_mtl_fc_active() local
117 u32 reg_val; sxgbe_mtl_fc_enable() local
127 u32 reg_val; sxgbe_mtl_fc_deactive() local
138 u32 reg_val; sxgbe_mtl_fep_enable() local
148 u32 reg_val; sxgbe_mtl_fep_disable() local
158 u32 reg_val; sxgbe_mtl_fup_enable() local
168 u32 reg_val; sxgbe_mtl_fup_disable() local
180 u32 reg_val; sxgbe_set_tx_mtl_mode() local
211 u32 reg_val; sxgbe_set_rx_mtl_mode() local
[all...]
/kernel/linux/linux-6.6/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_mtl.c23 u32 reg_val; in sxgbe_mtl_init() local
25 reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
26 reg_val &= ETS_RST; in sxgbe_mtl_init()
31 reg_val &= ETS_WRR; in sxgbe_mtl_init()
34 reg_val |= ETS_WFQ; in sxgbe_mtl_init()
37 reg_val |= ETS_DWRR; in sxgbe_mtl_init()
40 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
44 reg_val &= RAA_SP; in sxgbe_mtl_init()
47 reg_val |= RAA_WSP; in sxgbe_mtl_init()
50 writel(reg_val, ioadd in sxgbe_mtl_init()
64 u32 fifo_bits, reg_val; sxgbe_mtl_set_txfifosize() local
76 u32 fifo_bits, reg_val; sxgbe_mtl_set_rxfifosize() local
87 u32 reg_val; sxgbe_mtl_enable_txqueue() local
96 u32 reg_val; sxgbe_mtl_disable_txqueue() local
106 u32 reg_val; sxgbe_mtl_fc_active() local
117 u32 reg_val; sxgbe_mtl_fc_enable() local
127 u32 reg_val; sxgbe_mtl_fc_deactive() local
138 u32 reg_val; sxgbe_mtl_fep_enable() local
148 u32 reg_val; sxgbe_mtl_fep_disable() local
158 u32 reg_val; sxgbe_mtl_fup_enable() local
168 u32 reg_val; sxgbe_mtl_fup_disable() local
180 u32 reg_val; sxgbe_set_tx_mtl_mode() local
211 u32 reg_val; sxgbe_set_rx_mtl_mode() local
[all...]
/kernel/linux/linux-5.10/drivers/input/keyboard/
H A Dimx_keypad.c82 unsigned short reg_val; in imx_keypad_scan_matrix() local
93 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
94 reg_val |= 0xff00; in imx_keypad_scan_matrix()
95 writew(reg_val, keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
97 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
98 reg_val &= ~((keypad->cols_en_mask & 0xff) << 8); in imx_keypad_scan_matrix()
99 writew(reg_val, keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
103 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
104 reg_val |= (keypad->cols_en_mask & 0xff) << 8; in imx_keypad_scan_matrix()
105 writew(reg_val, keypa in imx_keypad_scan_matrix()
187 unsigned short reg_val; imx_keypad_check_for_events() local
290 unsigned short reg_val; imx_keypad_irq_handler() local
314 unsigned short reg_val; imx_keypad_config() local
350 unsigned short reg_val; imx_keypad_inhibit() local
530 unsigned short reg_val = readw(kbd->mmio_base + KPSR); imx_kbd_noirq_suspend() local
[all...]
/kernel/linux/linux-6.6/drivers/input/keyboard/
H A Dimx_keypad.c83 unsigned short reg_val; in imx_keypad_scan_matrix() local
94 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
95 reg_val |= 0xff00; in imx_keypad_scan_matrix()
96 writew(reg_val, keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
98 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
99 reg_val &= ~((keypad->cols_en_mask & 0xff) << 8); in imx_keypad_scan_matrix()
100 writew(reg_val, keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
104 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
105 reg_val |= (keypad->cols_en_mask & 0xff) << 8; in imx_keypad_scan_matrix()
106 writew(reg_val, keypa in imx_keypad_scan_matrix()
188 unsigned short reg_val; imx_keypad_check_for_events() local
291 unsigned short reg_val; imx_keypad_irq_handler() local
315 unsigned short reg_val; imx_keypad_config() local
351 unsigned short reg_val; imx_keypad_inhibit() local
522 unsigned short reg_val = readw(kbd->mmio_base + KPSR); imx_kbd_noirq_suspend() local
[all...]
/kernel/linux/linux-6.6/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_cn9k_pf.c266 u64 reg_val; in octep_setup_iq_regs_cn93_pf() local
269 reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no)); in octep_setup_iq_regs_cn93_pf()
272 if (!(reg_val & CN93_R_IN_CTL_IDLE)) { in octep_setup_iq_regs_cn93_pf()
274 reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no)); in octep_setup_iq_regs_cn93_pf()
275 } while (!(reg_val & CN93_R_IN_CTL_IDLE)); in octep_setup_iq_regs_cn93_pf()
278 reg_val |= CN93_R_IN_CTL_RDSIZE; in octep_setup_iq_regs_cn93_pf()
279 reg_val |= CN93_R_IN_CTL_IS_64B; in octep_setup_iq_regs_cn93_pf()
280 reg_val |= CN93_R_IN_CTL_ESR; in octep_setup_iq_regs_cn93_pf()
281 octep_write_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no), reg_val); in octep_setup_iq_regs_cn93_pf()
304 reg_val in octep_setup_iq_regs_cn93_pf()
311 u64 reg_val; octep_setup_oq_regs_cn93_pf() local
407 u64 reg_val = 0; octep_non_ioq_intr_handler_cn93_pf() local
613 u64 reg_val; octep_enable_iq_cn93_pf() local
636 u64 reg_val = 0ULL; octep_enable_oq_cn93_pf() local
665 u64 reg_val = 0ULL; octep_disable_iq_cn93_pf() local
677 u64 reg_val = 0ULL; octep_disable_oq_cn93_pf() local
[all...]
/kernel/linux/linux-6.6/drivers/spi/
H A Dspi-mt65xx.c271 u32 reg_val; in mtk_spi_reset() local
274 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
275 reg_val |= SPI_CMD_RST; in mtk_spi_reset()
276 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
278 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
279 reg_val &= ~SPI_CMD_RST; in mtk_spi_reset()
280 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
290 u32 reg_val; in mtk_spi_set_hw_cs_timing() local
309 reg_val = readl(mdata->base + SPI_CFG0_REG); in mtk_spi_set_hw_cs_timing()
313 reg_val in mtk_spi_set_hw_cs_timing()
354 u32 reg_val; mtk_spi_hw_init() local
463 u32 reg_val; mtk_spi_set_cs() local
484 u32 div, sck_time, reg_val; mtk_spi_prepare_transfer() local
516 u32 packet_size, packet_loop, reg_val; mtk_spi_setup_packet() local
628 u32 reg_val; mtk_spi_fifo_transfer() local
703 u32 reg_val = 0; mtk_spi_transfer_one() local
747 u32 cmd, reg_val, cnt, remainder, len; mtk_spi_interrupt() local
947 u32 reg_val, nio, tx_size; mtk_spi_mem_exec_op() local
[all...]
H A Dspi-slave-mt27xx.c100 u32 reg_val; in mtk_spi_slave_disable_dma() local
102 reg_val = readl(mdata->base + SPIS_DMA_CFG_REG); in mtk_spi_slave_disable_dma()
103 reg_val &= ~RX_DMA_EN; in mtk_spi_slave_disable_dma()
104 reg_val &= ~TX_DMA_EN; in mtk_spi_slave_disable_dma()
105 writel(reg_val, mdata->base + SPIS_DMA_CFG_REG); in mtk_spi_slave_disable_dma()
110 u32 reg_val; in mtk_spi_slave_disable_xfer() local
112 reg_val = readl(mdata->base + SPIS_CFG_REG); in mtk_spi_slave_disable_xfer()
113 reg_val &= ~SPIS_TX_EN; in mtk_spi_slave_disable_xfer()
114 reg_val &= ~SPIS_RX_EN; in mtk_spi_slave_disable_xfer()
115 writel(reg_val, mdat in mtk_spi_slave_disable_xfer()
135 u32 reg_val; mtk_spi_slave_prepare_message() local
167 int reg_val, cnt, remainder, ret; mtk_spi_slave_fifo_transfer() local
205 int reg_val, ret; mtk_spi_slave_dma_transfer() local
301 u32 reg_val; mtk_spi_slave_setup() local
332 u32 int_status, reg_val, cnt, remainder; mtk_spi_slave_interrupt() local
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_vbif.c61 u32 reg_val; in dpu_hw_set_mem_type() local
79 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_mem_type()
80 reg_val &= ~(0x7 << bit_off); in dpu_hw_set_mem_type()
81 reg_val |= (value & 0x7) << bit_off; in dpu_hw_set_mem_type()
82 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_mem_type()
89 u32 reg_val; in dpu_hw_set_limit_conf() local
100 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_limit_conf()
101 reg_val &= ~(0xFF << bit_off); in dpu_hw_set_limit_conf()
102 reg_val |= (limit) << bit_off; in dpu_hw_set_limit_conf()
103 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_limit_conf()
110 u32 reg_val; dpu_hw_get_limit_conf() local
132 u32 reg_val; dpu_hw_set_halt_ctrl() local
148 u32 reg_val; dpu_hw_get_halt_ctrl() local
159 u32 reg_lvl, reg_val, reg_val_lvl, mask, reg_high, reg_shift; dpu_hw_set_qos_remap() local
188 u32 reg_val; dpu_hw_set_write_gather_en() local
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/
H A Ddc_helper.c146 uint32_t reg_val) in dmub_reg_value_burst_set_pack()
164 cmd_buf->write_values[offload->reg_seq_count] = reg_val; in dmub_reg_value_burst_set_pack()
229 uint32_t reg_val; in generic_reg_update_ex() local
245 reg_val = dm_read_reg(ctx, addr); in generic_reg_update_ex()
246 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; in generic_reg_update_ex()
247 dm_write_reg(ctx, addr, reg_val); in generic_reg_update_ex()
248 return reg_val; in generic_reg_update_ex()
252 uint32_t addr, uint32_t reg_val, int n, in generic_reg_set_ex()
268 reg_val in generic_reg_set_ex()
145 dmub_reg_value_burst_set_pack(const struct dc_context *ctx, uint32_t addr, uint32_t reg_val) dmub_reg_value_burst_set_pack() argument
251 generic_reg_set_ex(const struct dc_context *ctx, uint32_t addr, uint32_t reg_val, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) generic_reg_set_ex() argument
283 uint32_t reg_val = dm_read_reg(ctx, addr); generic_reg_get() local
292 uint32_t reg_val = dm_read_reg(ctx, addr); generic_reg_get2() local
303 uint32_t reg_val = dm_read_reg(ctx, addr); generic_reg_get3() local
316 uint32_t reg_val = dm_read_reg(ctx, addr); generic_reg_get4() local
331 uint32_t reg_val = dm_read_reg(ctx, addr); generic_reg_get5() local
348 uint32_t reg_val = dm_read_reg(ctx, addr); generic_reg_get6() local
367 uint32_t reg_val = dm_read_reg(ctx, addr); generic_reg_get7() local
388 uint32_t reg_val = dm_read_reg(ctx, addr); generic_reg_get8() local
436 uint32_t reg_val; generic_reg_wait() local
539 generic_indirect_reg_update_ex(const struct dc_context *ctx, uint32_t addr_index, uint32_t addr_data, uint32_t index, uint32_t reg_val, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) generic_indirect_reg_update_ex() argument
570 generic_indirect_reg_update_ex_sync(const struct dc_context *ctx, uint32_t index, uint32_t reg_val, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) generic_indirect_reg_update_ex_sync() argument
[all...]
/kernel/linux/linux-5.10/drivers/spi/
H A Dspi-slave-mt27xx.c83 u32 reg_val; in mtk_spi_slave_disable_dma() local
85 reg_val = readl(mdata->base + SPIS_DMA_CFG_REG); in mtk_spi_slave_disable_dma()
86 reg_val &= ~RX_DMA_EN; in mtk_spi_slave_disable_dma()
87 reg_val &= ~TX_DMA_EN; in mtk_spi_slave_disable_dma()
88 writel(reg_val, mdata->base + SPIS_DMA_CFG_REG); in mtk_spi_slave_disable_dma()
93 u32 reg_val; in mtk_spi_slave_disable_xfer() local
95 reg_val = readl(mdata->base + SPIS_CFG_REG); in mtk_spi_slave_disable_xfer()
96 reg_val &= ~SPIS_TX_EN; in mtk_spi_slave_disable_xfer()
97 reg_val &= ~SPIS_RX_EN; in mtk_spi_slave_disable_xfer()
98 writel(reg_val, mdat in mtk_spi_slave_disable_xfer()
118 u32 reg_val; mtk_spi_slave_prepare_message() local
150 int reg_val, cnt, remainder, ret; mtk_spi_slave_fifo_transfer() local
188 int reg_val, ret; mtk_spi_slave_dma_transfer() local
284 u32 reg_val; mtk_spi_slave_setup() local
315 u32 int_status, reg_val, cnt, remainder; mtk_spi_slave_interrupt() local
[all...]
H A Dspi-mt65xx.c183 u32 reg_val; in mtk_spi_reset() local
186 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
187 reg_val |= SPI_CMD_RST; in mtk_spi_reset()
188 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
190 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
191 reg_val &= ~SPI_CMD_RST; in mtk_spi_reset()
192 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
199 u32 reg_val; in mtk_spi_prepare_message() local
207 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_prepare_message()
209 reg_val | in mtk_spi_prepare_message()
269 u32 reg_val; mtk_spi_set_cs() local
290 u32 spi_clk_hz, div, sck_time, cs_time, reg_val; mtk_spi_prepare_transfer() local
330 u32 packet_size, packet_loop, reg_val; mtk_spi_setup_packet() local
427 u32 reg_val; mtk_spi_fifo_transfer() local
532 u32 cmd, reg_val, cnt, remainder, len; mtk_spi_interrupt() local
[all...]
/kernel/linux/linux-5.10/sound/drivers/opl3/
H A Dopl3_synth.c396 unsigned char reg_val; in snd_opl3_play_note() local
416 reg_val = (unsigned char) note->fnum; in snd_opl3_play_note()
418 opl3->command(opl3, opl3_reg, reg_val); in snd_opl3_play_note()
420 reg_val = 0x00; in snd_opl3_play_note()
423 reg_val |= OPL3_KEYON_BIT; in snd_opl3_play_note()
425 reg_val |= (note->octave << 2) & OPL3_BLOCKNUM_MASK; in snd_opl3_play_note()
427 reg_val |= (unsigned char) (note->fnum >> 8) & OPL3_FNUM_HIGH_MASK; in snd_opl3_play_note()
431 opl3->command(opl3, opl3_reg, reg_val); in snd_opl3_play_note()
444 unsigned char reg_val; in snd_opl3_set_voice() local
470 reg_val in snd_opl3_set_voice()
543 unsigned char reg_val; snd_opl3_set_params() local
595 unsigned char reg_val; snd_opl3_set_connection() local
[all...]
/kernel/linux/linux-6.6/sound/drivers/opl3/
H A Dopl3_synth.c396 unsigned char reg_val; in snd_opl3_play_note() local
416 reg_val = (unsigned char) note->fnum; in snd_opl3_play_note()
418 opl3->command(opl3, opl3_reg, reg_val); in snd_opl3_play_note()
420 reg_val = 0x00; in snd_opl3_play_note()
423 reg_val |= OPL3_KEYON_BIT; in snd_opl3_play_note()
425 reg_val |= (note->octave << 2) & OPL3_BLOCKNUM_MASK; in snd_opl3_play_note()
427 reg_val |= (unsigned char) (note->fnum >> 8) & OPL3_FNUM_HIGH_MASK; in snd_opl3_play_note()
431 opl3->command(opl3, opl3_reg, reg_val); in snd_opl3_play_note()
444 unsigned char reg_val; in snd_opl3_set_voice() local
470 reg_val in snd_opl3_set_voice()
543 unsigned char reg_val; snd_opl3_set_params() local
595 unsigned char reg_val; snd_opl3_set_connection() local
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/
H A Ddc_helper.c165 uint32_t reg_val) in dmub_reg_value_burst_set_pack()
183 cmd_buf->write_values[offload->reg_seq_count] = reg_val; in dmub_reg_value_burst_set_pack()
248 uint32_t reg_val; in generic_reg_update_ex() local
264 reg_val = dm_read_reg(ctx, addr); in generic_reg_update_ex()
265 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; in generic_reg_update_ex()
266 dm_write_reg(ctx, addr, reg_val); in generic_reg_update_ex()
267 return reg_val; in generic_reg_update_ex()
271 uint32_t addr, uint32_t reg_val, int n, in generic_reg_set_ex()
287 reg_val in generic_reg_set_ex()
164 dmub_reg_value_burst_set_pack(const struct dc_context *ctx, uint32_t addr, uint32_t reg_val) dmub_reg_value_burst_set_pack() argument
270 generic_reg_set_ex(const struct dc_context *ctx, uint32_t addr, uint32_t reg_val, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) generic_reg_set_ex() argument
328 uint32_t reg_val = dm_read_reg(ctx, addr); generic_reg_get() local
337 uint32_t reg_val = dm_read_reg(ctx, addr); generic_reg_get2() local
348 uint32_t reg_val = dm_read_reg(ctx, addr); generic_reg_get3() local
361 uint32_t reg_val = dm_read_reg(ctx, addr); generic_reg_get4() local
376 uint32_t reg_val = dm_read_reg(ctx, addr); generic_reg_get5() local
393 uint32_t reg_val = dm_read_reg(ctx, addr); generic_reg_get6() local
412 uint32_t reg_val = dm_read_reg(ctx, addr); generic_reg_get7() local
433 uint32_t reg_val = dm_read_reg(ctx, addr); generic_reg_get8() local
481 uint32_t reg_val; generic_reg_wait() local
586 generic_indirect_reg_update_ex(const struct dc_context *ctx, uint32_t addr_index, uint32_t addr_data, uint32_t index, uint32_t reg_val, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) generic_indirect_reg_update_ex() argument
[all...]
/kernel/linux/linux-6.6/arch/riscv/kvm/
H A Dvcpu_onereg.c127 unsigned long reg_val; in kvm_riscv_vcpu_get_reg_config() local
134 reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK; in kvm_riscv_vcpu_get_reg_config()
139 reg_val = riscv_cbom_block_size; in kvm_riscv_vcpu_get_reg_config()
144 reg_val = riscv_cboz_block_size; in kvm_riscv_vcpu_get_reg_config()
147 reg_val = vcpu->arch.mvendorid; in kvm_riscv_vcpu_get_reg_config()
150 reg_val = vcpu->arch.marchid; in kvm_riscv_vcpu_get_reg_config()
153 reg_val = vcpu->arch.mimpid; in kvm_riscv_vcpu_get_reg_config()
156 reg_val = satp_mode >> SATP_MODE_SHIFT; in kvm_riscv_vcpu_get_reg_config()
162 if (copy_to_user(uaddr, &reg_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_config()
176 unsigned long i, isa_ext, reg_val; in kvm_riscv_vcpu_set_reg_config() local
281 unsigned long reg_val; kvm_riscv_vcpu_get_reg_core() local
314 unsigned long reg_val; kvm_riscv_vcpu_set_reg_core() local
359 kvm_riscv_vcpu_general_set_csr(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long reg_val) kvm_riscv_vcpu_general_set_csr() argument
390 unsigned long reg_val, reg_subtype; kvm_riscv_vcpu_get_reg_csr() local
426 unsigned long reg_val, reg_subtype; kvm_riscv_vcpu_set_reg_csr() local
453 riscv_vcpu_get_isa_ext_single(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long *reg_val) riscv_vcpu_get_isa_ext_single() argument
474 riscv_vcpu_set_isa_ext_single(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long reg_val) riscv_vcpu_set_isa_ext_single() argument
512 riscv_vcpu_get_isa_ext_multi(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long *reg_val) riscv_vcpu_get_isa_ext_multi() argument
535 riscv_vcpu_set_isa_ext_multi(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long reg_val, bool enable) riscv_vcpu_set_isa_ext_multi() argument
564 unsigned long reg_val, reg_subtype; kvm_riscv_vcpu_get_reg_isa_ext() local
603 unsigned long reg_val, reg_subtype; kvm_riscv_vcpu_set_reg_isa_ext() local
[all...]
/kernel/linux/linux-5.10/drivers/net/ethernet/allwinner/
H A Dsun4i-emac.c95 unsigned int reg_val; in emac_update_speed() local
98 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
99 reg_val &= ~(0x1 << 8); in emac_update_speed()
101 reg_val |= 1 << 8; in emac_update_speed()
102 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
108 unsigned int reg_val; in emac_update_duplex() local
111 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
112 reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN; in emac_update_duplex()
114 reg_val |= EMAC_MAC_CTL1_DUPLEX_EN; in emac_update_duplex()
115 writel(reg_val, d in emac_update_duplex()
243 unsigned int reg_val; emac_setup() local
286 unsigned int reg_val; emac_set_rx_mode() local
306 unsigned int reg_val; emac_powerup() local
374 unsigned int reg_val; emac_init_device() local
503 unsigned int reg_val; emac_rx() local
643 unsigned int reg_val; emac_interrupt() local
731 unsigned int reg_val; emac_shutdown() local
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_vbif.c61 u32 reg_val; in dpu_hw_set_mem_type() local
79 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_mem_type()
80 reg_val &= ~(0x7 << bit_off); in dpu_hw_set_mem_type()
81 reg_val |= (value & 0x7) << bit_off; in dpu_hw_set_mem_type()
82 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_mem_type()
89 u32 reg_val; in dpu_hw_set_limit_conf() local
100 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_limit_conf()
101 reg_val &= ~(0xFF << bit_off); in dpu_hw_set_limit_conf()
102 reg_val |= (limit) << bit_off; in dpu_hw_set_limit_conf()
103 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_limit_conf()
110 u32 reg_val; dpu_hw_get_limit_conf() local
132 u32 reg_val; dpu_hw_set_halt_ctrl() local
148 u32 reg_val; dpu_hw_get_halt_ctrl() local
159 u32 reg_val, reg_val_lvl, mask, reg_high, reg_shift; dpu_hw_set_qos_remap() local
187 u32 reg_val; dpu_hw_set_write_gather_en() local
[all...]
/kernel/linux/linux-6.6/arch/arm/mach-qcom/
H A Dplatsmp.c84 u32 reg_val; in cortex_a7_release_secondary() local
103 reg_val = CORE_RST | COREPOR_RST | CLAMP | CORE_MEM_CLAMP; in cortex_a7_release_secondary()
104 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
111 reg_val &= ~CORE_MEM_CLAMP; in cortex_a7_release_secondary()
112 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
113 reg_val |= L2DT_SLP; in cortex_a7_release_secondary()
114 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
117 reg_val = (reg_val | BIT(17)) & ~CLAMP; in cortex_a7_release_secondary()
118 writel(reg_val, re in cortex_a7_release_secondary()
219 unsigned reg_val; kpssv2_release_secondary() local
[all...]
/kernel/linux/linux-5.10/arch/powerpc/platforms/powernv/
H A Dopal-fadump.h83 __be64 reg_val; member
88 u64 reg_val) in opal_fadump_set_regval_regnum()
92 regs->gpr[reg_num] = reg_val; in opal_fadump_set_regval_regnum()
98 regs->ctr = reg_val; in opal_fadump_set_regval_regnum()
101 regs->link = reg_val; in opal_fadump_set_regval_regnum()
104 regs->xer = reg_val; in opal_fadump_set_regval_regnum()
107 regs->dar = reg_val; in opal_fadump_set_regval_regnum()
110 regs->dsisr = reg_val; in opal_fadump_set_regval_regnum()
113 regs->nip = reg_val; in opal_fadump_set_regval_regnum()
116 regs->msr = reg_val; in opal_fadump_set_regval_regnum()
86 opal_fadump_set_regval_regnum(struct pt_regs *regs, u32 reg_type, u32 reg_num, u64 reg_val) opal_fadump_set_regval_regnum() argument
[all...]
/kernel/linux/linux-6.6/arch/powerpc/platforms/powernv/
H A Dopal-fadump.h83 __be64 reg_val; member
88 u64 reg_val) in opal_fadump_set_regval_regnum()
92 regs->gpr[reg_num] = reg_val; in opal_fadump_set_regval_regnum()
98 regs->ctr = reg_val; in opal_fadump_set_regval_regnum()
101 regs->link = reg_val; in opal_fadump_set_regval_regnum()
104 regs->xer = reg_val; in opal_fadump_set_regval_regnum()
107 regs->dar = reg_val; in opal_fadump_set_regval_regnum()
110 regs->dsisr = reg_val; in opal_fadump_set_regval_regnum()
113 regs->nip = reg_val; in opal_fadump_set_regval_regnum()
116 regs->msr = reg_val; in opal_fadump_set_regval_regnum()
86 opal_fadump_set_regval_regnum(struct pt_regs *regs, u32 reg_type, u32 reg_num, u64 reg_val) opal_fadump_set_regval_regnum() argument
[all...]
/kernel/linux/linux-6.6/drivers/net/ethernet/allwinner/
H A Dsun4i-emac.c105 unsigned int reg_val; in emac_update_speed() local
108 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
109 reg_val &= ~EMAC_MAC_SUPP_100M; in emac_update_speed()
111 reg_val |= EMAC_MAC_SUPP_100M; in emac_update_speed()
112 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
118 unsigned int reg_val; in emac_update_duplex() local
121 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
122 reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN; in emac_update_duplex()
124 reg_val |= EMAC_MAC_CTL1_DUPLEX_EN; in emac_update_duplex()
125 writel(reg_val, d in emac_update_duplex()
250 u32 reg_val; emac_dma_done_callback() local
364 unsigned int reg_val; emac_setup() local
407 unsigned int reg_val; emac_set_rx_mode() local
427 unsigned int reg_val; emac_powerup() local
495 unsigned int reg_val; emac_init_device() local
623 unsigned int reg_val; emac_rx() local
764 unsigned int reg_val; emac_interrupt() local
857 unsigned int reg_val; emac_shutdown() local
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_hdcp.c45 u32 reg_val; member
199 u32 reg_val, hdcp_int_status; in msm_hdmi_hdcp_irq() local
203 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_INT_CTRL); in msm_hdmi_hdcp_irq()
204 hdcp_int_status = reg_val & HDCP_INT_STATUS_MASK; in msm_hdmi_hdcp_irq()
210 reg_val |= hdcp_int_status << 1; in msm_hdmi_hdcp_irq()
213 reg_val |= HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK; in msm_hdmi_hdcp_irq()
214 hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, reg_val); in msm_hdmi_hdcp_irq()
228 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS); in msm_hdmi_hdcp_irq()
230 __func__, reg_val); in msm_hdmi_hdcp_irq()
284 u32 reg_val, failur in msm_reset_hdcp_ddc_failures() local
402 u32 reg_val; msm_hdmi_hdcp_reauth_work() local
459 u32 reg_val; msm_hdmi_hdcp_auth_prepare() local
540 u32 reg_val; msm_hdmi_hdcp_auth_fail() local
558 u32 reg_val; msm_hdmi_hdcp_auth_done() local
1120 u32 reg_val, data, reg; msm_hdmi_hdcp_write_ksv_fifo() local
1307 u32 reg_val; msm_hdmi_hdcp_on() local
1333 u32 reg_val; msm_hdmi_hdcp_off() local
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_hdcp.c45 u32 reg_val; member
199 u32 reg_val, hdcp_int_status; in msm_hdmi_hdcp_irq() local
203 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_INT_CTRL); in msm_hdmi_hdcp_irq()
204 hdcp_int_status = reg_val & HDCP_INT_STATUS_MASK; in msm_hdmi_hdcp_irq()
210 reg_val |= hdcp_int_status << 1; in msm_hdmi_hdcp_irq()
213 reg_val |= HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK; in msm_hdmi_hdcp_irq()
214 hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, reg_val); in msm_hdmi_hdcp_irq()
228 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS); in msm_hdmi_hdcp_irq()
230 __func__, reg_val); in msm_hdmi_hdcp_irq()
284 u32 reg_val, failur in msm_reset_hdcp_ddc_failures() local
402 u32 reg_val; msm_hdmi_hdcp_reauth_work() local
459 u32 reg_val; msm_hdmi_hdcp_auth_prepare() local
540 u32 reg_val; msm_hdmi_hdcp_auth_fail() local
558 u32 reg_val; msm_hdmi_hdcp_auth_done() local
1120 u32 reg_val, data, reg; msm_hdmi_hdcp_write_ksv_fifo() local
1307 u32 reg_val; msm_hdmi_hdcp_on() local
1333 u32 reg_val; msm_hdmi_hdcp_off() local
[all...]
/kernel/linux/linux-5.10/arch/mips/pci/
H A Dfixup-malta.c70 unsigned char reg_val; in malta_piix_func0_fixup() local
84 pci_read_config_byte(pdev, PIIX4_FUNC0_PIRQRC+i, &reg_val); in malta_piix_func0_fixup()
85 if (reg_val & PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE) in malta_piix_func0_fixup()
88 pci_irq[PCIA+i] = piixirqmap[reg_val & in malta_piix_func0_fixup()
98 pci_read_config_byte(pdev, PIIX4_FUNC0_TOM, &reg_val); in malta_piix_func0_fixup()
99 pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val | in malta_piix_func0_fixup()
109 pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val); in malta_piix_func0_fixup()
110 reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT; in malta_piix_func0_fixup()
111 pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val); in malta_piix_func0_fixup()
124 unsigned char reg_val; in malta_piix_func1_fixup() local
[all...]
/kernel/linux/linux-6.6/arch/mips/pci/
H A Dfixup-malta.c70 unsigned char reg_val; in malta_piix_func0_fixup() local
84 pci_read_config_byte(pdev, PIIX4_FUNC0_PIRQRC+i, &reg_val); in malta_piix_func0_fixup()
85 if (reg_val & PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE) in malta_piix_func0_fixup()
88 pci_irq[PCIA+i] = piixirqmap[reg_val & in malta_piix_func0_fixup()
98 pci_read_config_byte(pdev, PIIX4_FUNC0_TOM, &reg_val); in malta_piix_func0_fixup()
99 pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val | in malta_piix_func0_fixup()
109 pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val); in malta_piix_func0_fixup()
110 reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT; in malta_piix_func0_fixup()
111 pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val); in malta_piix_func0_fixup()
124 unsigned char reg_val; in malta_piix_func1_fixup() local
[all...]

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