Lines Matching refs:reg_val

183 	u32 reg_val;
186 	reg_val = readl(mdata->base + SPI_CMD_REG);
187 	reg_val |= SPI_CMD_RST;
188 	writel(reg_val, mdata->base + SPI_CMD_REG);
190 	reg_val = readl(mdata->base + SPI_CMD_REG);
191 	reg_val &= ~SPI_CMD_RST;
192 	writel(reg_val, mdata->base + SPI_CMD_REG);
199 	u32 reg_val;
207 	reg_val = readl(mdata->base + SPI_CMD_REG);
209 		reg_val |= SPI_CMD_CPHA;
211 		reg_val &= ~SPI_CMD_CPHA;
213 		reg_val |= SPI_CMD_CPOL;
215 		reg_val &= ~SPI_CMD_CPOL;
219 		reg_val &= ~SPI_CMD_TXMSBF;
220 		reg_val &= ~SPI_CMD_RXMSBF;
222 		reg_val |= SPI_CMD_TXMSBF;
223 		reg_val |= SPI_CMD_RXMSBF;
228 	reg_val &= ~SPI_CMD_TX_ENDIAN;
229 	reg_val &= ~SPI_CMD_RX_ENDIAN;
231 	reg_val |= SPI_CMD_TX_ENDIAN;
232 	reg_val |= SPI_CMD_RX_ENDIAN;
238 			reg_val |= SPI_CMD_CS_POL;
240 			reg_val &= ~SPI_CMD_CS_POL;
243 			reg_val |= SPI_CMD_SAMPLE_SEL;
245 			reg_val &= ~SPI_CMD_SAMPLE_SEL;
249 	reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
252 	reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
255 	reg_val &= ~SPI_CMD_DEASSERT;
257 	writel(reg_val, mdata->base + SPI_CMD_REG);
269 	u32 reg_val;
275 	reg_val = readl(mdata->base + SPI_CMD_REG);
277 		reg_val |= SPI_CMD_PAUSE_EN;
278 		writel(reg_val, mdata->base + SPI_CMD_REG);
280 		reg_val &= ~SPI_CMD_PAUSE_EN;
281 		writel(reg_val, mdata->base + SPI_CMD_REG);
290 	u32 spi_clk_hz, div, sck_time, cs_time, reg_val;
303 		reg_val = (((sck_time - 1) & 0xffff)
305 		reg_val |= (((sck_time - 1) & 0xffff)
307 		writel(reg_val, mdata->base + SPI_CFG2_REG);
308 		reg_val = (((cs_time - 1) & 0xffff)
310 		reg_val |= (((cs_time - 1) & 0xffff)
312 		writel(reg_val, mdata->base + SPI_CFG0_REG);
314 		reg_val = (((sck_time - 1) & 0xff)
316 		reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
317 		reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
318 		reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);
319 		writel(reg_val, mdata->base + SPI_CFG0_REG);
322 	reg_val = readl(mdata->base + SPI_CFG1_REG);
323 	reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
324 	reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
325 	writel(reg_val, mdata->base + SPI_CFG1_REG);
330 	u32 packet_size, packet_loop, reg_val;
336 	reg_val = readl(mdata->base + SPI_CFG1_REG);
337 	reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
338 	reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
339 	reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
340 	writel(reg_val, mdata->base + SPI_CFG1_REG);
427 	u32 reg_val;
441 			reg_val = 0;
442 			memcpy(&reg_val, xfer->tx_buf + (cnt * 4), remainder);
443 			writel(reg_val, mdata->base + SPI_TX_DATA_REG);
532 	u32 cmd, reg_val, cnt, remainder, len;
537 	reg_val = readl(mdata->base + SPI_STATUS0_REG);
538 	if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
550 				reg_val = readl(mdata->base + SPI_RX_DATA_REG);
554 					&reg_val,
575 			reg_val = 0;
576 			memcpy(&reg_val,
579 			writel(reg_val, mdata->base + SPI_TX_DATA_REG);