Lines Matching refs:reg_val
95 unsigned int reg_val;
98 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG);
99 reg_val &= ~(0x1 << 8);
101 reg_val |= 1 << 8;
102 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG);
108 unsigned int reg_val;
111 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG);
112 reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN;
114 reg_val |= EMAC_MAC_CTL1_DUPLEX_EN;
115 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG);
243 unsigned int reg_val;
246 reg_val = readl(db->membase + EMAC_TX_MODE_REG);
248 writel(reg_val | EMAC_TX_MODE_ABORTED_FRAME_EN,
253 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG);
254 writel(reg_val | EMAC_MAC_CTL0_RX_FLOW_CTL_EN |
259 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG);
260 reg_val |= EMAC_MAC_CTL1_LEN_CHECK_EN;
261 reg_val |= EMAC_MAC_CTL1_CRC_EN;
262 reg_val |= EMAC_MAC_CTL1_PAD_EN;
263 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG);
286 unsigned int reg_val;
289 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
292 reg_val |= EMAC_RX_CTL_PASS_ALL_EN;
294 reg_val &= ~EMAC_RX_CTL_PASS_ALL_EN;
296 writel(reg_val | EMAC_RX_CTL_PASS_LEN_OOR_EN |
306 unsigned int reg_val;
310 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
311 reg_val |= 0x8;
312 writel(reg_val, db->membase + EMAC_RX_CTL_REG);
317 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG);
318 reg_val &= ~EMAC_MAC_CTL0_SOFT_RESET;
319 writel(reg_val, db->membase + EMAC_MAC_CTL0_REG);
322 reg_val = readl(db->membase + EMAC_MAC_MCFG_REG);
323 reg_val &= (~(0xf << 2));
324 reg_val |= (0xD << 2);
325 writel(reg_val, db->membase + EMAC_MAC_MCFG_REG);
332 reg_val = readl(db->membase + EMAC_INT_STA_REG);
333 writel(reg_val, db->membase + EMAC_INT_STA_REG);
374 unsigned int reg_val;
382 reg_val = readl(db->membase + EMAC_CTL_REG);
383 writel(reg_val | EMAC_CTL_RESET | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN,
387 reg_val = readl(db->membase + EMAC_INT_CTL_REG);
388 reg_val |= (0xf << 0) | (0x01 << 8);
389 writel(reg_val, db->membase + EMAC_INT_CTL_REG);
503 unsigned int reg_val;
528 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
529 reg_val &= ~EMAC_RX_CTL_DMA_EN;
530 writel(reg_val, db->membase + EMAC_RX_CTL_REG);
535 reg_val = readl(db->membase + EMAC_INT_CTL_REG);
536 reg_val |= (0xf << 0) | (0x01 << 8);
537 writel(reg_val, db->membase + EMAC_INT_CTL_REG);
545 reg_val = readl(db->membase + EMAC_RX_IO_DATA_REG);
547 dev_dbg(db->dev, "receive header: %x\n", reg_val);
548 if (reg_val != EMAC_UNDOCUMENTED_MAGIC) {
550 reg_val = readl(db->membase + EMAC_CTL_REG);
551 writel(reg_val & ~EMAC_CTL_RX_EN,
555 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
556 writel(reg_val | (1 << 3),
560 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
561 } while (reg_val & (1 << 3));
564 reg_val = readl(db->membase + EMAC_CTL_REG);
565 writel(reg_val | EMAC_CTL_RX_EN,
567 reg_val = readl(db->membase + EMAC_INT_CTL_REG);
568 reg_val |= (0xf << 0) | (0x01 << 8);
569 writel(reg_val, db->membase + EMAC_INT_CTL_REG);
643 unsigned int reg_val;
677 reg_val = readl(db->membase + EMAC_INT_CTL_REG);
678 reg_val |= (0xf << 0) | (0x01 << 8);
679 writel(reg_val, db->membase + EMAC_INT_CTL_REG);
731 unsigned int reg_val;
738 reg_val = readl(db->membase + EMAC_INT_STA_REG);
739 writel(reg_val, db->membase + EMAC_INT_STA_REG);
742 reg_val = readl(db->membase + EMAC_CTL_REG);
743 reg_val &= ~(EMAC_CTL_TX_EN | EMAC_CTL_RX_EN | EMAC_CTL_RESET);
744 writel(reg_val, db->membase + EMAC_CTL_REG);