Lines Matching refs:reg_val
84 u32 reg_val;
103 reg_val = CORE_RST | COREPOR_RST | CLAMP | CORE_MEM_CLAMP;
104 writel(reg_val, reg + APCS_CPU_PWR_CTL);
111 reg_val &= ~CORE_MEM_CLAMP;
112 writel(reg_val, reg + APCS_CPU_PWR_CTL);
113 reg_val |= L2DT_SLP;
114 writel(reg_val, reg + APCS_CPU_PWR_CTL);
117 reg_val = (reg_val | BIT(17)) & ~CLAMP;
118 writel(reg_val, reg + APCS_CPU_PWR_CTL);
122 reg_val &= ~(CORE_RST | COREPOR_RST);
123 writel(reg_val, reg + APCS_CPU_PWR_CTL);
124 reg_val |= CORE_PWRD_UP;
125 writel(reg_val, reg + APCS_CPU_PWR_CTL);
219 unsigned reg_val;
257 reg_val = (64 << BHS_CNT_SHIFT) | (0x3f << LDO_PWR_DWN_SHIFT) | BHS_EN;
258 writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
264 reg_val |= 0x3f << BHS_SEG_SHIFT;
265 writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
271 reg_val |= 0x3f << LDO_BYP_SHIFT;
272 writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
279 reg_val = COREPOR_RST | CLAMP;
280 writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
284 reg_val &= ~CLAMP;
285 writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
289 reg_val &= ~COREPOR_RST;
290 writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
293 reg_val |= CORE_PWRD_UP;
294 writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);