Lines Matching refs:reg_val

271 	u32 reg_val;
274 	reg_val = readl(mdata->base + SPI_CMD_REG);
275 	reg_val |= SPI_CMD_RST;
276 	writel(reg_val, mdata->base + SPI_CMD_REG);
278 	reg_val = readl(mdata->base + SPI_CMD_REG);
279 	reg_val &= ~SPI_CMD_RST;
280 	writel(reg_val, mdata->base + SPI_CMD_REG);
290 	u32 reg_val;
309 		reg_val = readl(mdata->base + SPI_CFG0_REG);
313 				reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
314 				reg_val |= (((hold - 1) & 0xffff)
319 				reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
320 				reg_val |= (((setup - 1) & 0xffff)
326 				reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET);
327 				reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
331 				reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET);
332 				reg_val |= (((setup - 1) & 0xff)
336 		writel(reg_val, mdata->base + SPI_CFG0_REG);
341 		reg_val = readl(mdata->base + SPI_CFG1_REG);
342 		reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
343 		reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
344 		writel(reg_val, mdata->base + SPI_CFG1_REG);
354 	u32 reg_val;
361 	reg_val = readl(mdata->base + SPI_CMD_REG);
364 		reg_val |= SPI_CMD_IPM_NONIDLE_MODE;
366 			reg_val |= SPI_CMD_IPM_SPIM_LOOP;
368 			reg_val &= ~SPI_CMD_IPM_SPIM_LOOP;
372 		reg_val |= SPI_CMD_CPHA;
374 		reg_val &= ~SPI_CMD_CPHA;
376 		reg_val |= SPI_CMD_CPOL;
378 		reg_val &= ~SPI_CMD_CPOL;
382 		reg_val &= ~SPI_CMD_TXMSBF;
383 		reg_val &= ~SPI_CMD_RXMSBF;
385 		reg_val |= SPI_CMD_TXMSBF;
386 		reg_val |= SPI_CMD_RXMSBF;
391 	reg_val &= ~SPI_CMD_TX_ENDIAN;
392 	reg_val &= ~SPI_CMD_RX_ENDIAN;
394 	reg_val |= SPI_CMD_TX_ENDIAN;
395 	reg_val |= SPI_CMD_RX_ENDIAN;
401 			reg_val |= SPI_CMD_CS_POL;
403 			reg_val &= ~SPI_CMD_CS_POL;
406 			reg_val |= SPI_CMD_SAMPLE_SEL;
408 			reg_val &= ~SPI_CMD_SAMPLE_SEL;
412 	reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
415 	reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
418 	reg_val &= ~SPI_CMD_DEASSERT;
420 	writel(reg_val, mdata->base + SPI_CMD_REG);
430 			reg_val = readl(mdata->base + SPI_CMD_REG);
431 			reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;
432 			reg_val |= ((chip_config->tick_delay & 0x7)
434 			writel(reg_val, mdata->base + SPI_CMD_REG);
436 			reg_val = readl(mdata->base + SPI_CFG1_REG);
437 			reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
438 			reg_val |= ((chip_config->tick_delay & 0x7)
440 			writel(reg_val, mdata->base + SPI_CFG1_REG);
443 		reg_val = readl(mdata->base + SPI_CFG1_REG);
444 		reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
445 		reg_val |= ((chip_config->tick_delay & 0x3)
447 		writel(reg_val, mdata->base + SPI_CFG1_REG);
463 	u32 reg_val;
469 	reg_val = readl(mdata->base + SPI_CMD_REG);
471 		reg_val |= SPI_CMD_PAUSE_EN;
472 		writel(reg_val, mdata->base + SPI_CMD_REG);
474 		reg_val &= ~SPI_CMD_PAUSE_EN;
475 		writel(reg_val, mdata->base + SPI_CMD_REG);
484 	u32 div, sck_time, reg_val;
495 		reg_val = readl(mdata->base + SPI_CFG2_REG);
496 		reg_val &= ~(0xffff << SPI_CFG2_SCK_HIGH_OFFSET);
497 		reg_val |= (((sck_time - 1) & 0xffff)
499 		reg_val &= ~(0xffff << SPI_CFG2_SCK_LOW_OFFSET);
500 		reg_val |= (((sck_time - 1) & 0xffff)
502 		writel(reg_val, mdata->base + SPI_CFG2_REG);
504 		reg_val = readl(mdata->base + SPI_CFG0_REG);
505 		reg_val &= ~(0xff << SPI_CFG0_SCK_HIGH_OFFSET);
506 		reg_val |= (((sck_time - 1) & 0xff)
508 		reg_val &= ~(0xff << SPI_CFG0_SCK_LOW_OFFSET);
509 		reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
510 		writel(reg_val, mdata->base + SPI_CFG0_REG);
516 	u32 packet_size, packet_loop, reg_val;
530 	reg_val = readl(mdata->base + SPI_CFG1_REG);
532 		reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK;
534 		reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK;
535 	reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
536 	reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK;
537 	reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
538 	writel(reg_val, mdata->base + SPI_CFG1_REG);
628 	u32 reg_val;
642 			reg_val = 0;
643 			memcpy(&reg_val, xfer->tx_buf + (cnt * 4), remainder);
644 			writel(reg_val, mdata->base + SPI_TX_DATA_REG);
703 	u32 reg_val = 0;
708 			reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;
710 				reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;
712 		writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);
747 	u32 cmd, reg_val, cnt, remainder, len;
752 	reg_val = readl(mdata->base + SPI_STATUS0_REG);
753 	if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
771 				reg_val = readl(mdata->base + SPI_RX_DATA_REG);
775 					&reg_val,
797 				reg_val = 0;
798 				memcpy(&reg_val,
801 				writel(reg_val, mdata->base + SPI_TX_DATA_REG);
947 	u32 reg_val, nio, tx_size;
958 	reg_val = readl(mdata->base + SPI_CFG3_IPM_REG);
960 	reg_val &= ~SPI_CFG3_IPM_CMD_BYTELEN_MASK;
961 	reg_val |= 1 << SPI_CFG3_IPM_CMD_BYTELEN_OFFSET;
964 	reg_val &= ~SPI_CFG3_IPM_ADDR_BYTELEN_MASK;
966 		reg_val |= (op->addr.nbytes + op->dummy.nbytes) <<
971 		reg_val |= SPI_CFG3_IPM_NODATA_FLAG;
974 		reg_val &= ~SPI_CFG3_IPM_NODATA_FLAG;
981 			reg_val |= SPI_CFG3_IPM_XMODE_EN;
983 			reg_val &= ~SPI_CFG3_IPM_XMODE_EN;
997 	reg_val &= ~SPI_CFG3_IPM_CMD_PIN_MODE_MASK;
998 	reg_val |= PIN_MODE_CFG(nio);
1000 	reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;
1002 		reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;
1004 		reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR;
1005 	writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);
1068 	reg_val = readl(mdata->base + SPI_CMD_REG);
1069 	reg_val |= SPI_CMD_TX_DMA;
1071 		reg_val |= SPI_CMD_RX_DMA;
1072 	writel(reg_val, mdata->base + SPI_CMD_REG);
1084 	reg_val = readl(mdata->base + SPI_CMD_REG);
1085 	reg_val &= ~SPI_CMD_TX_DMA;
1087 		reg_val &= ~SPI_CMD_RX_DMA;
1088 	writel(reg_val, mdata->base + SPI_CMD_REG);