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/third_party/node/deps/v8/src/logging/
H A Dcounters-scopes.h49 base::ElapsedTimer timer_;
135 base::TimeTicks now = base::TimeTicks::Now(); in StartInteral()
142 base::TimeTicks now = base::TimeTicks::Now(); in StopInternal()
143 base::TimeDelta elapsed = timer_.Elapsed(now); in StopInternal()
164 void Pause(base::TimeTicks now) { in Pause()
169 void Resume(base::TimeTicks now) { in Resume()
174 void RecordLongTaskTime(base::TimeDelta elapsed) const { in RecordLongTaskTime()
197 previous_scope_->Pause(base in PauseNestedTimedHistogramScope()
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/third_party/mesa3d/src/gallium/drivers/etnaviv/
H A Detnaviv_surface.c100 surf->base.context = pctx; in etna_create_surface()
102 pipe_reference_init(&surf->base.reference, 1); in etna_create_surface()
103 pipe_resource_reference(&surf->base.texture, &rsc->base); in etna_create_surface()
121 surf->base.format = templat->format; in etna_create_surface()
122 surf->base.width = rsc->levels[level].width; in etna_create_surface()
123 surf->base.height = rsc->levels[level].height; in etna_create_surface()
124 surf->base.writable = templat->writable; /* what is this for anyway */ in etna_create_surface()
125 surf->base.u = templat->u; in etna_create_surface()
168 struct etna_bo *ts_bo = etna_resource(surf->base in etna_create_surface()
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/kernel/linux/linux-5.10/drivers/clk/renesas/
H A Drenesas-cpg-mssr.c126 * @base: CPG/MSSR register block base address
147 void __iomem *base; member
202 value = readb(priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
207 writeb(value, priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
210 readb(priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
211 barrier_data(priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
213 value = readl(priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
218 writel(value, priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
227 if (!(readl(priv->base in cpg_mstp_clock_endisable()
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H A Drcar-gen2-cpg.c138 void __iomem *base) in cpg_z_clk_register()
154 zclk->reg = base + CPG_FRQCRC; in cpg_z_clk_register()
155 zclk->kick_reg = base + CPG_FRQCRB; in cpg_z_clk_register()
167 void __iomem *base) in cpg_rcan_clk_register()
186 gate->reg = base + CPG_RCANCKCR; in cpg_rcan_clk_register()
211 void __iomem *base) in cpg_adsp_clk_register()
221 div->reg = base + CPG_ADSPCKCR; in cpg_adsp_clk_register()
232 gate->reg = base + CPG_ADSPCKCR; in cpg_adsp_clk_register()
278 struct clk **clks, void __iomem *base, in rcar_gen2_cpg_clk_register()
310 u32 pll0cr = readl(base in rcar_gen2_cpg_clk_register()
136 cpg_z_clk_register(const char *name, const char *parent_name, void __iomem *base) cpg_z_clk_register() argument
165 cpg_rcan_clk_register(const char *name, const char *parent_name, void __iomem *base) cpg_rcan_clk_register() argument
209 cpg_adsp_clk_register(const char *name, const char *parent_name, void __iomem *base) cpg_adsp_clk_register() argument
276 rcar_gen2_cpg_clk_register(struct device *dev, const struct cpg_core_clk *core, const struct cpg_mssr_info *info, struct clk **clks, void __iomem *base, struct raw_notifier_head *notifiers) rcar_gen2_cpg_clk_register() argument
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/kernel/linux/linux-5.10/arch/mips/include/asm/
H A Dasmmacro.h261 .macro ld_b wd, off, base
266 ld.b $w\wd, \off(\base)
270 .macro ld_h wd, off, base
275 ld.h $w\wd, \off(\base)
279 .macro ld_w wd, off, base
284 ld.w $w\wd, \off(\base)
288 .macro ld_d wd, off, base
293 ld.d $w\wd, \off(\base)
297 .macro st_b wd, off, base
302 st.b $w\wd, \off(\base)
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/kernel/linux/linux-6.6/arch/mips/include/asm/
H A Dasmmacro.h261 .macro ld_b wd, off, base
266 ld.b $w\wd, \off(\base)
270 .macro ld_h wd, off, base
275 ld.h $w\wd, \off(\base)
279 .macro ld_w wd, off, base
284 ld.w $w\wd, \off(\base)
288 .macro ld_d wd, off, base
293 ld.d $w\wd, \off(\base)
297 .macro st_b wd, off, base
302 st.b $w\wd, \off(\base)
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/kernel/linux/linux-5.10/drivers/net/ethernet/qlogic/netxen/
H A Dnetxen_nic_ethtool.c104 cmd->base.port = PORT_TP; in netxen_nic_get_link_ksettings()
106 cmd->base.speed = adapter->link_speed; in netxen_nic_get_link_ksettings()
107 cmd->base.duplex = adapter->link_duplex; in netxen_nic_get_link_ksettings()
108 cmd->base.autoneg = adapter->link_autoneg; in netxen_nic_get_link_ksettings()
123 cmd->base.speed = adapter->link_speed; in netxen_nic_get_link_ksettings()
124 cmd->base.autoneg = adapter->link_autoneg; in netxen_nic_get_link_ksettings()
125 cmd->base.duplex = adapter->link_duplex; in netxen_nic_get_link_ksettings()
129 cmd->base.port = PORT_TP; in netxen_nic_get_link_ksettings()
135 cmd->base.speed = P3_LINK_SPEED_MHZ * in netxen_nic_get_link_ksettings()
138 cmd->base in netxen_nic_get_link_ksettings()
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/kernel/linux/linux-5.10/drivers/power/supply/
H A Dsc27xx_fuel_gauge.c76 * @base: the base offset for the controller
101 u32 base; member
157 data->base + SC27XX_FGU_USER_AREA_STATUS, &status); in sc27xx_fgu_is_first_poweron()
185 data->base + SC27XX_FGU_USER_AREA_CLEAR, in sc27xx_fgu_save_boot_mode()
200 data->base + SC27XX_FGU_USER_AREA_SET, in sc27xx_fgu_save_boot_mode()
220 data->base + SC27XX_FGU_USER_AREA_CLEAR, in sc27xx_fgu_save_boot_mode()
229 data->base + SC27XX_FGU_USER_AREA_CLEAR, in sc27xx_fgu_save_last_cap()
244 data->base + SC27XX_FGU_USER_AREA_SET, in sc27xx_fgu_save_last_cap()
263 data->base in sc27xx_fgu_save_last_cap()
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/kernel/linux/linux-6.6/drivers/net/ethernet/qlogic/netxen/
H A Dnetxen_nic_ethtool.c104 cmd->base.port = PORT_TP; in netxen_nic_get_link_ksettings()
106 cmd->base.speed = adapter->link_speed; in netxen_nic_get_link_ksettings()
107 cmd->base.duplex = adapter->link_duplex; in netxen_nic_get_link_ksettings()
108 cmd->base.autoneg = adapter->link_autoneg; in netxen_nic_get_link_ksettings()
123 cmd->base.speed = adapter->link_speed; in netxen_nic_get_link_ksettings()
124 cmd->base.autoneg = adapter->link_autoneg; in netxen_nic_get_link_ksettings()
125 cmd->base.duplex = adapter->link_duplex; in netxen_nic_get_link_ksettings()
129 cmd->base.port = PORT_TP; in netxen_nic_get_link_ksettings()
135 cmd->base.speed = P3_LINK_SPEED_MHZ * in netxen_nic_get_link_ksettings()
138 cmd->base in netxen_nic_get_link_ksettings()
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/kernel/linux/linux-6.6/drivers/tty/serial/
H A Drp2.c184 void __iomem *base; member
236 u32 tmp = readl(up->base + reg); in rp2_rmw()
239 writel(tmp, up->base + reg); in rp2_rmw()
280 tx_fifo_bytes = readw(up->base + RP2_TX_FIFO_COUNT); in rp2_uart_tx_empty()
291 status = readl(up->base + RP2_CHAN_STAT); in rp2_uart_get_mctrl()
343 writew(baud_div - 1, up->base + RP2_BAUD); in __rp2_uart_set_termios()
399 u16 bytes = readw(up->base + RP2_RX_FIFO_COUNT); in rp2_rx_chars()
403 u32 byte = readw(up->base + RP2_DATA_BYTE) | RP2_DUMMY_READ; in rp2_rx_chars()
433 FIFO_SIZE - readw(up->base + RP2_TX_FIFO_COUNT), in rp2_tx_chars()
435 writeb(ch, up->base in rp2_tx_chars()
464 void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id); rp2_asic_interrupt() local
577 void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id); rp2_reset_asic() local
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/kernel/linux/linux-6.6/drivers/power/supply/
H A Dsc27xx_fuel_gauge.c76 * @base: the base offset for the controller
101 u32 base; member
157 data->base + SC27XX_FGU_USER_AREA_STATUS, &status); in sc27xx_fgu_is_first_poweron()
185 data->base + SC27XX_FGU_USER_AREA_CLEAR, in sc27xx_fgu_save_boot_mode()
200 data->base + SC27XX_FGU_USER_AREA_SET, in sc27xx_fgu_save_boot_mode()
220 data->base + SC27XX_FGU_USER_AREA_CLEAR, in sc27xx_fgu_save_boot_mode()
229 data->base + SC27XX_FGU_USER_AREA_CLEAR, in sc27xx_fgu_save_last_cap()
244 data->base + SC27XX_FGU_USER_AREA_SET, in sc27xx_fgu_save_last_cap()
263 data->base in sc27xx_fgu_save_last_cap()
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/kernel/linux/linux-6.6/drivers/media/i2c/ccs/
H A Dccs-data.c17 void *base; member
45 bin->base = bin->now = kvzalloc(bin->size, GFP_KERNEL); in bin_backing_alloc()
46 if (!bin->base) in bin_backing_alloc()
49 bin->end = bin->base + bin->size; in bin_backing_alloc()
141 if (!bin->base) { in ccs_data_parse_version()
221 if (bin->base && __regs) { in ccs_data_parse_regs()
285 if (!bin->base) { in ccs_data_parse_regs()
305 if (!bin->base) in ccs_data_parse_regs()
311 if (bin->base && __regs) { in ccs_data_parse_regs()
329 if (!bin->base) in ccs_data_parse_reg_rules()
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/kernel/linux/linux-6.6/drivers/perf/
H A Dcxl_pmu.c97 void __iomem *base; member
127 void __iomem *base = info->base; in cxl_pmu_parse_caps() local
132 val = readq(base + CXL_PMU_CAP_REG); in cxl_pmu_parse_caps()
156 val = readq(base + CXL_PMU_COUNTER_CFG_REG(i)); in cxl_pmu_parse_caps()
170 eval = readq(base + CXL_PMU_EVENT_CAP_REG(group_idx)); in cxl_pmu_parse_caps()
199 eval = readq(base + CXL_PMU_EVENT_CAP_REG(j)); in cxl_pmu_parse_caps()
599 void __iomem *base = info->base; in cxl_pmu_enable() local
602 writeq(0, base in cxl_pmu_enable()
608 void __iomem *base = info->base; cxl_pmu_disable() local
624 void __iomem *base = info->base; cxl_pmu_event_start() local
687 void __iomem *base = info->base; cxl_pmu_read_counter() local
722 void __iomem *base = info->base; cxl_pmu_event_stop() local
778 void __iomem *base = info->base; cxl_pmu_irq() local
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H A Darm-ccn.c131 void __iomem *base; member
147 void __iomem *base; member
171 void __iomem *base; member
850 res = readq(ccn->dt.base + CCN_DT_PMCCNTR); in arm_ccn_pmu_read_counter()
853 writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ); in arm_ccn_pmu_read_counter()
854 while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1)) in arm_ccn_pmu_read_counter()
856 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR); in arm_ccn_pmu_read_counter()
857 res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff; in arm_ccn_pmu_read_counter()
859 res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR); in arm_ccn_pmu_read_counter()
862 res = readl(ccn->dt.base in arm_ccn_pmu_read_counter()
1335 arm_ccn_for_each_valid_region(struct arm_ccn *ccn, int (*callback)(struct arm_ccn *ccn, int region, void __iomem *base, u32 type, u32 id)) arm_ccn_for_each_valid_region() argument
1343 void __iomem *base; arm_ccn_for_each_valid_region() local
1366 arm_ccn_get_nodes_num(struct arm_ccn *ccn, int region, void __iomem *base, u32 type, u32 id) arm_ccn_get_nodes_num() argument
1378 arm_ccn_init_nodes(struct arm_ccn *ccn, int region, void __iomem *base, u32 type, u32 id) arm_ccn_init_nodes() argument
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/third_party/mesa3d/include/GL/internal/
H A Ddri_interface.h130 __DRIextension base; member
141 __DRIextension base; member
152 __DRIextension base; member
182 __DRIextension base; member
185 * Method to override base texture image with the contents of a
196 * Method to override base texture image with the contents of a
237 __DRIextension base; member
282 __DRIextension base; member
304 __DRIextension base; member
332 __DRIextension base; member
426 __DRIextension base; global() member
448 __DRIextension base; global() member
504 __DRIextension base; global() member
533 __DRIextension base; global() member
640 __DRIextension base; global() member
767 __DRIextension base; global() member
842 unsigned char *base; /**< Framebuffer base address in the CPU's global() member
866 __DRIextension base; global() member
979 __DRIextension base; global() member
1122 __DRIextension base; global() member
1362 __DRIextension base; global() member
1720 __DRIextension base; global() member
1756 __DRIextension base; global() member
1777 __DRIextension base; global() member
1793 __DRIextension base; global() member
1808 __DRIextension base; global() member
1828 __DRIextension base; global() member
1854 __DRIextension base; global() member
1898 __DRIextension base; global() member
1971 __DRIextension base; global() member
2046 __DRIextension base; global() member
2066 __DRIextension base; global() member
2149 __DRIextension base; global() member
2165 __DRIextension base; global() member
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/third_party/libdrm/nouveau/
H A Dnouveau.c399 dev = *pdev = &nvdev->base; in nouveau_device_new()
415 nvdev->base.chipset = info.chipset; in nouveau_device_new()
419 nvdev->base.object.parent = &drm->client; in nouveau_device_new()
420 nvdev->base.object.handle = ~0ULL; in nouveau_device_new()
421 nvdev->base.object.oclass = NOUVEAU_DEVICE_CLASS; in nouveau_device_new()
422 nvdev->base.object.length = ~0; in nouveau_device_new()
427 nvdev->base.chipset = v; in nouveau_device_new()
438 nvdev->base.vram_size = v; in nouveau_device_new()
443 nvdev->base.gart_size = v; in nouveau_device_new()
451 nvdev->base in nouveau_device_new()
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/kernel/linux/linux-5.10/drivers/perf/
H A Darm-ccn.c131 void __iomem *base; member
147 void __iomem *base; member
171 void __iomem *base; member
855 res = readq(ccn->dt.base + CCN_DT_PMCCNTR); in arm_ccn_pmu_read_counter()
858 writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ); in arm_ccn_pmu_read_counter()
859 while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1)) in arm_ccn_pmu_read_counter()
861 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR); in arm_ccn_pmu_read_counter()
862 res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff; in arm_ccn_pmu_read_counter()
864 res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR); in arm_ccn_pmu_read_counter()
867 res = readl(ccn->dt.base in arm_ccn_pmu_read_counter()
1342 arm_ccn_for_each_valid_region(struct arm_ccn *ccn, int (*callback)(struct arm_ccn *ccn, int region, void __iomem *base, u32 type, u32 id)) arm_ccn_for_each_valid_region() argument
1350 void __iomem *base; arm_ccn_for_each_valid_region() local
1373 arm_ccn_get_nodes_num(struct arm_ccn *ccn, int region, void __iomem *base, u32 type, u32 id) arm_ccn_get_nodes_num() argument
1385 arm_ccn_init_nodes(struct arm_ccn *ccn, int region, void __iomem *base, u32 type, u32 id) arm_ccn_init_nodes() argument
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/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_fb.c457 for (i = 0; i < plane->base.modifier_count; i++) in intel_fb_plane_supports_modifier()
458 if (plane->base.modifiers[i] == modifier) in intel_fb_plane_supports_modifier()
589 int main_plane = skl_ccs_to_main_plane(&fb->base, ccs_plane); in gen12_ccs_aux_stride()
590 unsigned int main_stride = fb->base.pitches[main_plane]; in gen12_ccs_aux_stride()
591 unsigned int main_tile_width = intel_tile_width_bytes(&fb->base, main_plane); in gen12_ccs_aux_stride()
895 int main_plane = intel_fb_is_ccs_aux_plane(&fb->base, color_plane) ? in intel_fb_plane_dims()
896 skl_ccs_to_main_plane(&fb->base, color_plane) : 0; in intel_fb_plane_dims()
897 unsigned int main_width = fb->base.width; in intel_fb_plane_dims()
898 unsigned int main_height = fb->base.height; in intel_fb_plane_dims()
902 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, &fb->base, main_plan in intel_fb_plane_dims()
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/kernel/linux/linux-5.10/arch/sparc/crypto/
H A Dcamellia_glue.c218 .base.cra_name = "ecb(camellia)",
219 .base.cra_driver_name = "ecb-camellia-sparc64",
220 .base.cra_priority = SPARC_CR_OPCODE_PRIORITY,
221 .base.cra_blocksize = CAMELLIA_BLOCK_SIZE,
222 .base.cra_ctxsize = sizeof(struct camellia_sparc64_ctx),
223 .base.cra_alignmask = 7,
224 .base.cra_module = THIS_MODULE,
231 .base.cra_name = "cbc(camellia)",
232 .base.cra_driver_name = "cbc-camellia-sparc64",
233 .base
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/kernel/linux/linux-5.10/arch/arm/mm/
H A Dpmsa-v7.c20 phys_addr_t base; member
66 /* Region base address register */
90 /* I-side Region base address register */
126 /* Region base address register */
146 static bool __init try_split_region(phys_addr_t base, phys_addr_t size, struct region *region) in try_split_region() argument
149 phys_addr_t abase = base & ~(size - 1); in try_split_region()
150 phys_addr_t asize = base + size - abase; in try_split_region()
157 bdiff = base - abase; in try_split_region()
183 region->base = abase; in try_split_region()
189 static int __init allocate_region(phys_addr_t base, phys_addr_ argument
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/kernel/linux/linux-5.10/drivers/gpio/
H A Dgpio-vf610.c33 void __iomem *base; member
120 return pinctrl_gpio_direction_input(chip->base + gpio); in vf610_gpio_direction_input()
138 return pinctrl_gpio_direction_output(chip->base + gpio); in vf610_gpio_direction_output()
151 irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR); in vf610_gpio_irq_handler()
154 vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR); in vf610_gpio_irq_handler()
168 vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR); in vf610_gpio_irq_ack()
211 void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq); in vf610_gpio_irq_mask()
220 void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq); in vf610_gpio_irq_unmask()
260 port->base = devm_platform_ioremap_resource(pdev, 0); in vf610_gpio_probe()
261 if (IS_ERR(port->base)) in vf610_gpio_probe()
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/kernel/linux/linux-6.6/arch/arm/mm/
H A Dpmsa-v7.c20 phys_addr_t base; member
66 /* Region base address register */
90 /* I-side Region base address register */
126 /* Region base address register */
146 static bool __init try_split_region(phys_addr_t base, phys_addr_t size, struct region *region) in try_split_region() argument
149 phys_addr_t abase = base & ~(size - 1); in try_split_region()
150 phys_addr_t asize = base + size - abase; in try_split_region()
157 bdiff = base - abase; in try_split_region()
183 region->base = abase; in try_split_region()
189 static int __init allocate_region(phys_addr_t base, phys_addr_ argument
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/kernel/linux/linux-6.6/arch/sparc/crypto/
H A Dcamellia_glue.c218 .base.cra_name = "ecb(camellia)",
219 .base.cra_driver_name = "ecb-camellia-sparc64",
220 .base.cra_priority = SPARC_CR_OPCODE_PRIORITY,
221 .base.cra_blocksize = CAMELLIA_BLOCK_SIZE,
222 .base.cra_ctxsize = sizeof(struct camellia_sparc64_ctx),
223 .base.cra_alignmask = 7,
224 .base.cra_module = THIS_MODULE,
231 .base.cra_name = "cbc(camellia)",
232 .base.cra_driver_name = "cbc-camellia-sparc64",
233 .base
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
H A Dselftest_engine_cs.c255 struct i915_vma *base, *nop; in perf_mi_noop() local
261 base = create_empty_batch(ce); in perf_mi_noop()
262 if (IS_ERR(base)) { in perf_mi_noop()
263 err = PTR_ERR(base); in perf_mi_noop()
268 err = i915_vma_sync(base); in perf_mi_noop()
270 i915_vma_put(base); in perf_mi_noop()
278 i915_vma_put(base); in perf_mi_noop()
286 i915_vma_put(base); in perf_mi_noop()
305 base->node.start, 8, in perf_mi_noop()
340 i915_vma_put(base); in perf_mi_noop()
377 u32 base = info->mmio_bases[j].base; intel_mmio_bases_check() local
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/kernel/linux/linux-5.10/drivers/irqchip/
H A Dirq-tegra.c69 void __iomem *base[TEGRA_MAX_NUM_ICTLRS]; member
84 void __iomem *base = (void __iomem __force *)d->chip_data; in tegra_ictlr_write_mask() local
88 writel_relaxed(mask, base + reg); in tegra_ictlr_write_mask()
142 void __iomem *ictlr = lic->base[i]; in tegra_ictlr_suspend()
171 void __iomem *ictlr = lic->base[i]; in tegra_ictlr_resume()
260 (void __force *)info->base[ictlr]); in tegra_ictlr_domain_alloc()
306 void __iomem *base; in tegra_ictlr_init() local
308 base = of_iomap(node, i); in tegra_ictlr_init()
309 if (!base) in tegra_ictlr_init()
312 lic->base[ in tegra_ictlr_init()
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