Lines Matching refs:base
131 void __iomem *base;
147 void __iomem *base;
171 void __iomem *base;
850 res = readq(ccn->dt.base + CCN_DT_PMCCNTR);
853 writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ);
854 while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1))
856 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
857 res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff;
859 res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR);
862 res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx));
908 val = readl(xp->base + CCN_XP_DT_CONFIG);
912 writel(val, xp->base + CCN_XP_DT_CONFIG);
959 val = readl(source->base + CCN_XP_DT_INTERFACE_SEL);
972 writel(val, source->base + CCN_XP_DT_INTERFACE_SEL);
975 writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp));
977 source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4);
978 writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp));
980 source->base + CCN_XP_DT_CMP_VAL_H(wp) + 4);
983 writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp));
985 source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4);
986 writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp));
988 source->base + CCN_XP_DT_CMP_MASK_H(wp) + 4);
1005 val = readl(source->base + CCN_XP_PMU_EVENT_SEL);
1009 writel(val, source->base + CCN_XP_PMU_EVENT_SEL);
1041 val = readl(source->base + CCN_HNF_PMU_EVENT_SEL);
1046 writel(val, source->base + CCN_HNF_PMU_EVENT_SEL);
1068 val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1072 writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1143 u32 val = readl(ccn->dt.base + CCN_DT_PMCR);
1145 writel(val, ccn->dt.base + CCN_DT_PMCR);
1152 u32 val = readl(ccn->dt.base + CCN_DT_PMCR);
1154 writel(val, ccn->dt.base + CCN_DT_PMCR);
1159 u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR);
1165 writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR);
1227 ccn->dt.base = ccn->base + CCN_REGION_SIZE;
1229 writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR);
1230 writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL);
1232 ccn->dt.base + CCN_DT_PMCR);
1233 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
1235 writel(0, ccn->xp[i].base + CCN_XP_DT_CONFIG);
1241 ccn->xp[i].base + CCN_XP_DT_CONTROL);
1317 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1318 writel(0, ccn->dt.base + CCN_DT_PMCR);
1329 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1330 writel(0, ccn->dt.base + CCN_DT_PMCR);
1337 void __iomem *base, u32 type, u32 id))
1343 void __iomem *base;
1346 val = readl(ccn->base + CCN_MN_OLY_COMP_LIST_63_0 +
1351 base = ccn->base + region * CCN_REGION_SIZE;
1352 val = readl(base + CCN_ALL_OLY_ID);
1358 err = callback(ccn, region, base, type, id);
1367 void __iomem *base, u32 type, u32 id)
1379 void __iomem *base, u32 type, u32 id)
1406 component->base = base;
1422 ccn->base + CCN_MN_ERRINT_STATUS);
1437 err_or = err_sig_val[0] = readl(ccn->base + CCN_MN_ERR_SIG_VAL_63_0);
1445 err_sig_val[i] = readl(ccn->base +
1454 ccn->base + CCN_MN_ERRINT_STATUS);
1472 ccn->base = devm_platform_ioremap_resource(pdev, 0);
1473 if (IS_ERR(ccn->base))
1474 return PTR_ERR(ccn->base);
1482 ccn->base + CCN_MN_ERRINT_STATUS);
1483 if (readl(ccn->base + CCN_MN_ERRINT_STATUS) &
1487 ccn->base + CCN_MN_ERRINT_STATUS);