Lines Matching refs:base
126 * @base: CPG/MSSR register block base address
147 void __iomem *base;
202 value = readb(priv->base + priv->control_regs[reg]);
207 writeb(value, priv->base + priv->control_regs[reg]);
210 readb(priv->base + priv->control_regs[reg]);
211 barrier_data(priv->base + priv->control_regs[reg]);
213 value = readl(priv->base + priv->control_regs[reg]);
218 writel(value, priv->base + priv->control_regs[reg]);
227 if (!(readl(priv->base + priv->status_regs[reg]) & bitmask))
234 priv->base + priv->control_regs[reg], bit);
258 value = readb(priv->base + priv->control_regs[clock->index / 32]);
260 value = readl(priv->base + priv->status_regs[clock->index / 32]);
362 div *= (readl(priv->base + core->offset) & 0x3f) + 1;
366 priv->base + core->offset,
383 priv->clks, priv->base,
602 writel(bitmask, priv->base + priv->reset_regs[reg]);
608 writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
622 writel(bitmask, priv->base + priv->reset_regs[reg]);
636 writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
648 return !!(readl(priv->base + priv->reset_regs[reg]) & bitmask);
857 readb(priv->base + priv->control_regs[reg]) :
858 readl(priv->base + priv->control_regs[reg]);
887 oldval = readb(priv->base + priv->control_regs[reg]);
889 oldval = readl(priv->base + priv->control_regs[reg]);
896 writeb(newval, priv->base + priv->control_regs[reg]);
898 readb(priv->base + priv->control_regs[reg]);
899 barrier_data(priv->base + priv->control_regs[reg]);
902 writel(newval, priv->base + priv->control_regs[reg]);
910 oldval = readl(priv->base + priv->status_regs[reg]);
956 priv->base = of_iomap(np, 0);
957 if (!priv->base) {
996 if (priv->base)
997 iounmap(priv->base);