Lines Matching refs:base
184 void __iomem *base;
236 u32 tmp = readl(up->base + reg);
239 writel(tmp, up->base + reg);
280 tx_fifo_bytes = readw(up->base + RP2_TX_FIFO_COUNT);
291 status = readl(up->base + RP2_CHAN_STAT);
343 writew(baud_div - 1, up->base + RP2_BAUD);
399 u16 bytes = readw(up->base + RP2_RX_FIFO_COUNT);
403 u32 byte = readw(up->base + RP2_DATA_BYTE) | RP2_DUMMY_READ;
433 FIFO_SIZE - readw(up->base + RP2_TX_FIFO_COUNT),
435 writeb(ch, up->base + RP2_DATA_BYTE),
449 status = readl(up->base + RP2_CHAN_STAT);
450 writel(status, up->base + RP2_CHAN_STAT);
464 void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id);
466 unsigned long status = readl(base + RP2_CH_IRQ_STAT) &
467 ~readl(base + RP2_CH_IRQ_MASK);
492 readl(up->base + RP2_UART_CTL);
577 void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id);
580 writew(1, base + RP2_GLOBAL_CMD);
581 readw(base + RP2_GLOBAL_CMD);
583 writel(0, base + RP2_CLK_PRESCALER);
586 clk_cfg = readw(base + RP2_ASIC_CFG);
588 writew(clk_cfg, base + RP2_ASIC_CFG);
591 writel(ALL_PORTS_MASK, base + RP2_CH_IRQ_MASK);
592 writel(RP2_ASIC_IRQ_EN_m, base + RP2_ASIC_IRQ);
611 writel(RP2_UART_CTL_RESET_CH_m, up->base + RP2_UART_CTL);
612 readl(up->base + RP2_UART_CTL);
615 writel(0, up->base + RP2_TXRX_CTL);
616 writel(0, up->base + RP2_UART_CTL);
617 readl(up->base + RP2_UART_CTL);
657 rp->base = card->bar1 + RP2_PORT_BASE + j*RP2_PORT_SPACING;
672 p->membase = rp->base;
677 rp->base += RP2_ASIC_SPACING;