Lines Matching refs:base
76 * @base: the base offset for the controller
101 u32 base;
157 data->base + SC27XX_FGU_USER_AREA_STATUS, &status);
185 data->base + SC27XX_FGU_USER_AREA_CLEAR,
200 data->base + SC27XX_FGU_USER_AREA_SET,
220 data->base + SC27XX_FGU_USER_AREA_CLEAR,
229 data->base + SC27XX_FGU_USER_AREA_CLEAR,
244 data->base + SC27XX_FGU_USER_AREA_SET,
263 data->base + SC27XX_FGU_USER_AREA_CLEAR,
272 data->base + SC27XX_FGU_USER_AREA_STATUS, &value);
308 ret = regmap_read(data->regmap, data->base + SC27XX_FGU_CLBCNT_QMAXL,
321 ret = regmap_read(data->regmap, data->base + SC27XX_FGU_POCV, &volt);
348 data->base + SC27XX_FGU_CLBCNT_SETL,
354 data->base + SC27XX_FGU_CLBCNT_SETH,
360 return regmap_update_bits(data->regmap, data->base + SC27XX_FGU_START,
369 ret = regmap_read(data->regmap, data->base + SC27XX_FGU_CLBCNT_VALL,
374 ret = regmap_read(data->regmap, data->base + SC27XX_FGU_CLBCNT_VALH,
390 ret = regmap_read(data->regmap, data->base + SC27XX_FGU_VOLTAGE_BUF,
409 ret = regmap_read(data->regmap, data->base + SC27XX_FGU_CURRENT_BUF,
458 ret = regmap_read(data->regmap, data->base + SC27XX_FGU_VOLTAGE, &vol);
475 ret = regmap_read(data->regmap, data->base + SC27XX_FGU_CURRENT, &cur);
870 data->base + SC27XX_FGU_LOW_OVERLOAD,
883 ret = regmap_read(data->regmap, data->base + SC27XX_FGU_INT_STS,
888 ret = regmap_update_bits(data->regmap, data->base + SC27XX_FGU_INT_CLR,
1065 ret = regmap_update_bits(data->regmap, data->base + SC27XX_FGU_INT_CLR,
1078 ret = regmap_update_bits(data->regmap, data->base + SC27XX_FGU_LOW_OVERLOAD,
1094 ret = regmap_update_bits(data->regmap, data->base + SC27XX_FGU_CLBCNT_DELTL,
1101 ret = regmap_update_bits(data->regmap, data->base + SC27XX_FGU_CLBCNT_DELTH,
1159 ret = device_property_read_u32(dev, "reg", &data->base);
1264 ret = regmap_update_bits(data->regmap, data->base + SC27XX_FGU_INT_EN,
1292 ret = regmap_update_bits(data->regmap, data->base + SC27XX_FGU_INT_EN,
1311 data->base + SC27XX_FGU_INT_EN,
1324 regmap_update_bits(data->regmap, data->base + SC27XX_FGU_INT_EN,