Lines Matching refs:base
131 void __iomem *base;
147 void __iomem *base;
171 void __iomem *base;
855 res = readq(ccn->dt.base + CCN_DT_PMCCNTR);
858 writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ);
859 while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1))
861 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
862 res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff;
864 res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR);
867 res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx));
913 val = readl(xp->base + CCN_XP_DT_CONFIG);
917 writel(val, xp->base + CCN_XP_DT_CONFIG);
964 val = readl(source->base + CCN_XP_DT_INTERFACE_SEL);
977 writel(val, source->base + CCN_XP_DT_INTERFACE_SEL);
980 writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp));
982 source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4);
983 writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp));
985 source->base + CCN_XP_DT_CMP_VAL_H(wp) + 4);
988 writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp));
990 source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4);
991 writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp));
993 source->base + CCN_XP_DT_CMP_MASK_H(wp) + 4);
1010 val = readl(source->base + CCN_XP_PMU_EVENT_SEL);
1014 writel(val, source->base + CCN_XP_PMU_EVENT_SEL);
1046 val = readl(source->base + CCN_HNF_PMU_EVENT_SEL);
1051 writel(val, source->base + CCN_HNF_PMU_EVENT_SEL);
1073 val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1077 writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1148 u32 val = readl(ccn->dt.base + CCN_DT_PMCR);
1150 writel(val, ccn->dt.base + CCN_DT_PMCR);
1157 u32 val = readl(ccn->dt.base + CCN_DT_PMCR);
1159 writel(val, ccn->dt.base + CCN_DT_PMCR);
1164 u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR);
1170 writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR);
1232 ccn->dt.base = ccn->base + CCN_REGION_SIZE;
1234 writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR);
1235 writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL);
1237 ccn->dt.base + CCN_DT_PMCR);
1238 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
1240 writel(0, ccn->xp[i].base + CCN_XP_DT_CONFIG);
1246 ccn->xp[i].base + CCN_XP_DT_CONTROL);
1322 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1323 writel(0, ccn->dt.base + CCN_DT_PMCR);
1336 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1337 writel(0, ccn->dt.base + CCN_DT_PMCR);
1344 void __iomem *base, u32 type, u32 id))
1350 void __iomem *base;
1353 val = readl(ccn->base + CCN_MN_OLY_COMP_LIST_63_0 +
1358 base = ccn->base + region * CCN_REGION_SIZE;
1359 val = readl(base + CCN_ALL_OLY_ID);
1365 err = callback(ccn, region, base, type, id);
1374 void __iomem *base, u32 type, u32 id)
1386 void __iomem *base, u32 type, u32 id)
1413 component->base = base;
1429 ccn->base + CCN_MN_ERRINT_STATUS);
1444 err_or = err_sig_val[0] = readl(ccn->base + CCN_MN_ERR_SIG_VAL_63_0);
1452 err_sig_val[i] = readl(ccn->base +
1461 ccn->base + CCN_MN_ERRINT_STATUS);
1480 ccn->base = devm_platform_ioremap_resource(pdev, 0);
1481 if (IS_ERR(ccn->base))
1482 return PTR_ERR(ccn->base);
1491 ccn->base + CCN_MN_ERRINT_STATUS);
1492 if (readl(ccn->base + CCN_MN_ERRINT_STATUS) &
1496 ccn->base + CCN_MN_ERRINT_STATUS);