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Searched refs:RREG32 (Results 1 - 25 of 336) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Dradeon_bios.c269 bus_cntl = RREG32(R600_BUS_CNTL); in ni_read_disabled_bios()
270 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); in ni_read_disabled_bios()
271 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); in ni_read_disabled_bios()
272 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); in ni_read_disabled_bios()
273 rom_cntl = RREG32(R600_ROM_CNTL); in ni_read_disabled_bios()
315 viph_control = RREG32(RADEON_VIPH_CONTROL); in r700_read_disabled_bios()
316 bus_cntl = RREG32(R600_BUS_CNTL); in r700_read_disabled_bios()
317 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); in r700_read_disabled_bios()
318 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); in r700_read_disabled_bios()
319 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTRO in r700_read_disabled_bios()
[all...]
H A Dvce_v2_0.c43 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
47 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
51 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
57 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
62 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
67 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
77 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_dyn_cg()
87 orig = tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_dyn_cg()
93 orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_dyn_cg()
134 tmp = RREG32(VCE_CLOCK_GATING_ in vce_v2_0_init_cg()
[all...]
H A Dradeon_legacy_encoders.c64 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_update()
92 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN); in radeon_legacy_lvds_update()
95 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); in radeon_legacy_lvds_update()
100 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); in radeon_legacy_lvds_update()
195 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); in radeon_legacy_lvds_mode_set()
198 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); in radeon_legacy_lvds_mode_set()
205 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_mode_set()
216 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_mode_set()
286 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> in radeon_legacy_get_backlight_level()
360 backlight_level = (RREG32(RADEON_LVDS_GEN_CNT in radeon_legacy_backlight_get_brightness()
[all...]
H A Dvce_v1_0.c63 return RREG32(VCE_RB_RPTR); in vce_v1_0_get_rptr()
65 return RREG32(VCE_RB_RPTR2); in vce_v1_0_get_rptr()
80 return RREG32(VCE_RB_WPTR); in vce_v1_0_get_wptr()
82 return RREG32(VCE_RB_WPTR2); in vce_v1_0_get_wptr()
107 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v1_0_enable_mgcg()
111 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v1_0_enable_mgcg()
116 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v1_0_enable_mgcg()
120 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v1_0_enable_mgcg()
124 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v1_0_enable_mgcg()
129 tmp = RREG32(VCE_UENC_REG_CLOCK_GATIN in vce_v1_0_enable_mgcg()
[all...]
H A Dradeon_i2c.c132 temp = RREG32(rec->mask_clk_reg); in pre_xfer()
138 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; in pre_xfer()
141 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; in pre_xfer()
145 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; in pre_xfer()
148 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; in pre_xfer()
152 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; in pre_xfer()
154 temp = RREG32(rec->mask_clk_reg); in pre_xfer()
156 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; in pre_xfer()
158 temp = RREG32(rec->mask_data_reg); in pre_xfer()
171 temp = RREG32(re in post_xfer()
[all...]
H A Drs600.c63 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) in avivo_is_in_vblank()
73 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
74 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
97 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) in avivo_wait_for_vblank()
121 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rs600_page_flip()
138 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rs600_page_flip()
154 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rs600_page_flip_pending()
232 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
241 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
327 tmp = RREG32(AVIVO_D1CRTC_CONTRO in rs600_pm_prepare()
[all...]
H A Drv730_dpm.c202 RREG32(CG_SPLL_FUNC_CNTL); in rv730_read_clock_registers()
204 RREG32(CG_SPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
206 RREG32(CG_SPLL_FUNC_CNTL_3); in rv730_read_clock_registers()
208 RREG32(CG_SPLL_SPREAD_SPECTRUM); in rv730_read_clock_registers()
210 RREG32(CG_SPLL_SPREAD_SPECTRUM_2); in rv730_read_clock_registers()
213 RREG32(TCI_MCLK_PWRMGT_CNTL); in rv730_read_clock_registers()
215 RREG32(TCI_DLL_CNTL); in rv730_read_clock_registers()
217 RREG32(CG_MPLL_FUNC_CNTL); in rv730_read_clock_registers()
219 RREG32(CG_MPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
221 RREG32(CG_MPLL_FUNC_CNTL_ in rv730_read_clock_registers()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Dradeon_bios.c269 bus_cntl = RREG32(R600_BUS_CNTL); in ni_read_disabled_bios()
270 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); in ni_read_disabled_bios()
271 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); in ni_read_disabled_bios()
272 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); in ni_read_disabled_bios()
273 rom_cntl = RREG32(R600_ROM_CNTL); in ni_read_disabled_bios()
315 viph_control = RREG32(RADEON_VIPH_CONTROL); in r700_read_disabled_bios()
316 bus_cntl = RREG32(R600_BUS_CNTL); in r700_read_disabled_bios()
317 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); in r700_read_disabled_bios()
318 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); in r700_read_disabled_bios()
319 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTRO in r700_read_disabled_bios()
[all...]
H A Dvce_v2_0.c44 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
48 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
52 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
58 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
63 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
68 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
78 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_dyn_cg()
88 orig = tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_dyn_cg()
94 orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_dyn_cg()
135 tmp = RREG32(VCE_CLOCK_GATING_ in vce_v2_0_init_cg()
[all...]
H A Dradeon_legacy_encoders.c67 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_update()
95 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN); in radeon_legacy_lvds_update()
98 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); in radeon_legacy_lvds_update()
103 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); in radeon_legacy_lvds_update()
198 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); in radeon_legacy_lvds_mode_set()
201 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); in radeon_legacy_lvds_mode_set()
208 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_mode_set()
219 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_mode_set()
289 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> in radeon_legacy_get_backlight_level()
361 backlight_level = (RREG32(RADEON_LVDS_GEN_CNT in radeon_legacy_backlight_get_brightness()
[all...]
H A Dvce_v1_0.c64 return RREG32(VCE_RB_RPTR); in vce_v1_0_get_rptr()
66 return RREG32(VCE_RB_RPTR2); in vce_v1_0_get_rptr()
81 return RREG32(VCE_RB_WPTR); in vce_v1_0_get_wptr()
83 return RREG32(VCE_RB_WPTR2); in vce_v1_0_get_wptr()
108 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v1_0_enable_mgcg()
112 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v1_0_enable_mgcg()
117 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v1_0_enable_mgcg()
121 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v1_0_enable_mgcg()
125 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v1_0_enable_mgcg()
130 tmp = RREG32(VCE_UENC_REG_CLOCK_GATIN in vce_v1_0_enable_mgcg()
[all...]
H A Dradeon_i2c.c124 temp = RREG32(rec->mask_clk_reg); in pre_xfer()
130 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; in pre_xfer()
133 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; in pre_xfer()
137 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; in pre_xfer()
140 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; in pre_xfer()
144 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; in pre_xfer()
146 temp = RREG32(rec->mask_clk_reg); in pre_xfer()
148 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; in pre_xfer()
150 temp = RREG32(rec->mask_data_reg); in pre_xfer()
163 temp = RREG32(re in post_xfer()
[all...]
H A Drs600.c65 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) in avivo_is_in_vblank()
75 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
76 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
99 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) in avivo_wait_for_vblank()
124 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rs600_page_flip()
145 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rs600_page_flip()
161 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rs600_page_flip_pending()
239 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
248 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
334 tmp = RREG32(AVIVO_D1CRTC_CONTRO in rs600_pm_prepare()
[all...]
H A Drv730_dpm.c200 RREG32(CG_SPLL_FUNC_CNTL); in rv730_read_clock_registers()
202 RREG32(CG_SPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
204 RREG32(CG_SPLL_FUNC_CNTL_3); in rv730_read_clock_registers()
206 RREG32(CG_SPLL_SPREAD_SPECTRUM); in rv730_read_clock_registers()
208 RREG32(CG_SPLL_SPREAD_SPECTRUM_2); in rv730_read_clock_registers()
211 RREG32(TCI_MCLK_PWRMGT_CNTL); in rv730_read_clock_registers()
213 RREG32(TCI_DLL_CNTL); in rv730_read_clock_registers()
215 RREG32(CG_MPLL_FUNC_CNTL); in rv730_read_clock_registers()
217 RREG32(CG_MPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
219 RREG32(CG_MPLL_FUNC_CNTL_ in rv730_read_clock_registers()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dgmc_v8_0.c176 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v8_0_mc_stop()
194 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v8_0_mc_resume()
243 if (RREG32(mmMC_SEQ_IO_DEBUG_DATA) == 0x05b4dc40) in gmc_v8_0_init_microcode()
305 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v8_0_tonga_mc_load_microcode()
328 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
334 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
374 data = RREG32(mmMC_SEQ_MISC0); in gmc_v8_0_polaris_mc_load_microcode()
398 data = RREG32(mmMC_SEQ_MISC0); in gmc_v8_0_polaris_mc_load_microcode()
413 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; in gmc_v8_0_vram_gtt_location()
448 tmp = RREG32(mmVGA_HDP_CONTRO in gmc_v8_0_mc_program()
[all...]
H A Dgmc_v7_0.c94 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v7_0_mc_stop()
112 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v7_0_mc_resume()
196 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v7_0_mc_load_microcode()
219 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
225 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
238 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; in gmc_v7_0_vram_gtt_location()
274 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v7_0_mc_program()
279 tmp = RREG32(mmVGA_RENDER_CONTROL); in gmc_v7_0_mc_program()
298 tmp = RREG32(mmHDP_MISC_CNTL); in gmc_v7_0_mc_program()
302 tmp = RREG32(mmHDP_HOST_PATH_CNT in gmc_v7_0_mc_program()
[all...]
H A Dvce_v2_0.c60 return RREG32(mmVCE_RB_RPTR); in vce_v2_0_ring_get_rptr()
62 return RREG32(mmVCE_RB_RPTR2); in vce_v2_0_ring_get_rptr()
77 return RREG32(mmVCE_RB_WPTR); in vce_v2_0_ring_get_wptr()
79 return RREG32(mmVCE_RB_WPTR2); in vce_v2_0_ring_get_wptr()
105 uint32_t status = RREG32(mmVCE_LMI_STATUS); in vce_v2_0_lmi_clean()
122 uint32_t status = RREG32(mmVCE_STATUS); in vce_v2_0_firmware_loaded()
151 tmp = RREG32(mmVCE_CLOCK_GATING_A); in vce_v2_0_init_cg()
157 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v2_0_init_cg()
162 tmp = RREG32(mmVCE_CLOCK_GATING_B); in vce_v2_0_init_cg()
208 return !(RREG32(mmSRBM_STATUS in vce_v2_0_is_idle()
[all...]
H A Diceland_ih.c62 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_enable_interrupts()
63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_enable_interrupts()
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_disable_interrupts()
82 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_disable_interrupts()
117 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in iceland_ih_irq_init()
148 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_irq_init()
201 wptr = RREG32(mmIH_RB_WPTR); in iceland_ih_get_wptr()
214 tmp = RREG32(mmIH_RB_CNTL); in iceland_ih_get_wptr()
347 u32 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_is_idle()
363 tmp = RREG32(mmSRBM_STATU in iceland_ih_wait_for_idle()
[all...]
H A Dcz_ih.c62 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_enable_interrupts()
63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_enable_interrupts()
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_disable_interrupts()
82 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_disable_interrupts()
117 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in cz_ih_irq_init()
148 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_irq_init()
201 wptr = RREG32(mmIH_RB_WPTR); in cz_ih_get_wptr()
215 tmp = RREG32(mmIH_RB_CNTL); in cz_ih_get_wptr()
353 u32 tmp = RREG32(mmSRBM_STATUS); in cz_ih_is_idle()
369 tmp = RREG32(mmSRBM_STATU in cz_ih_wait_for_idle()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dgmc_v8_0.c184 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v8_0_mc_stop()
202 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v8_0_mc_resume()
328 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v8_0_tonga_mc_load_microcode()
351 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
357 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
397 data = RREG32(mmMC_SEQ_MISC0); in gmc_v8_0_polaris_mc_load_microcode()
421 data = RREG32(mmMC_SEQ_MISC0); in gmc_v8_0_polaris_mc_load_microcode()
436 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; in gmc_v8_0_vram_gtt_location()
471 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v8_0_mc_program()
476 tmp = RREG32(mmVGA_RENDER_CONTRO in gmc_v8_0_mc_program()
[all...]
H A Dgmc_v7_0.c96 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v7_0_mc_stop()
114 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v7_0_mc_resume()
203 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v7_0_mc_load_microcode()
226 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
232 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
245 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; in gmc_v7_0_vram_gtt_location()
280 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v7_0_mc_program()
285 tmp = RREG32(mmVGA_RENDER_CONTROL); in gmc_v7_0_mc_program()
305 tmp = RREG32(mmHDP_MISC_CNTL); in gmc_v7_0_mc_program()
309 tmp = RREG32(mmHDP_HOST_PATH_CNT in gmc_v7_0_mc_program()
[all...]
H A Dvce_v2_0.c60 return RREG32(mmVCE_RB_RPTR); in vce_v2_0_ring_get_rptr()
62 return RREG32(mmVCE_RB_RPTR2); in vce_v2_0_ring_get_rptr()
77 return RREG32(mmVCE_RB_WPTR); in vce_v2_0_ring_get_wptr()
79 return RREG32(mmVCE_RB_WPTR2); in vce_v2_0_ring_get_wptr()
105 uint32_t status = RREG32(mmVCE_LMI_STATUS); in vce_v2_0_lmi_clean()
122 uint32_t status = RREG32(mmVCE_STATUS); in vce_v2_0_firmware_loaded()
151 tmp = RREG32(mmVCE_CLOCK_GATING_A); in vce_v2_0_init_cg()
157 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v2_0_init_cg()
162 tmp = RREG32(mmVCE_CLOCK_GATING_B); in vce_v2_0_init_cg()
208 return !(RREG32(mmSRBM_STATUS in vce_v2_0_is_idle()
[all...]
H A Diceland_ih.c62 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_enable_interrupts()
63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_enable_interrupts()
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_disable_interrupts()
82 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_disable_interrupts()
117 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in iceland_ih_irq_init()
148 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_irq_init()
200 wptr = RREG32(mmIH_RB_WPTR); in iceland_ih_get_wptr()
213 tmp = RREG32(mmIH_RB_CNTL); in iceland_ih_get_wptr()
344 u32 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_is_idle()
360 tmp = RREG32(mmSRBM_STATU in iceland_ih_wait_for_idle()
[all...]
H A Dcz_ih.c62 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_enable_interrupts()
63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_enable_interrupts()
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_disable_interrupts()
82 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_disable_interrupts()
117 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in cz_ih_irq_init()
148 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_irq_init()
200 wptr = RREG32(mmIH_RB_WPTR); in cz_ih_get_wptr()
214 tmp = RREG32(mmIH_RB_CNTL); in cz_ih_get_wptr()
345 u32 tmp = RREG32(mmSRBM_STATUS); in cz_ih_is_idle()
361 tmp = RREG32(mmSRBM_STATU in cz_ih_wait_for_idle()
[all...]
H A Dgmc_v6_0.c70 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v6_0_mc_stop()
89 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v6_0_mc_resume()
127 if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58) in gmc_v6_0_init_microcode()
174 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK; in gmc_v6_0_mc_load_microcode()
199 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK) in gmc_v6_0_mc_load_microcode()
204 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK) in gmc_v6_0_mc_load_microcode()
217 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; in gmc_v6_0_vram_gtt_location()
246 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v6_0_mc_program()
251 tmp = RREG32(mmVGA_RENDER_CONTROL); in gmc_v6_0_mc_program()
278 tmp = RREG32(mmMC_ARB_RAMCF in gmc_v6_0_mc_init()
[all...]

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