Lines Matching refs:RREG32
202 RREG32(CG_SPLL_FUNC_CNTL);
204 RREG32(CG_SPLL_FUNC_CNTL_2);
206 RREG32(CG_SPLL_FUNC_CNTL_3);
208 RREG32(CG_SPLL_SPREAD_SPECTRUM);
210 RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
213 RREG32(TCI_MCLK_PWRMGT_CNTL);
215 RREG32(TCI_DLL_CNTL);
217 RREG32(CG_MPLL_FUNC_CNTL);
219 RREG32(CG_MPLL_FUNC_CNTL_2);
221 RREG32(CG_MPLL_FUNC_CNTL_3);
223 RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM);
225 RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM_2);
402 arb_refresh_rate = RREG32(MC_ARB_RFSH_RATE) &
411 old_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
412 old_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
418 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
419 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
428 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
429 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
438 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
439 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
481 mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0);
487 mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0);
502 mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0);
505 mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0);