Lines Matching refs:RREG32
63 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
73 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
74 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
97 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
121 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
138 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
154 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
232 tmp = RREG32(voltage->gpio.reg);
241 tmp = RREG32(voltage->gpio.reg);
327 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
345 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
360 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
365 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
383 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
391 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
462 status = RREG32(R_000E40_RBBM_STATUS);
468 status = RREG32(R_000E40_RBBM_STATUS);
472 tmp = RREG32(RADEON_CP_RB_CNTL);
484 RREG32(R_0000F0_RBBM_SOFT_RESET);
488 status = RREG32(R_000E40_RBBM_STATUS);
492 RREG32(R_0000F0_RBBM_SOFT_RESET);
496 status = RREG32(R_000E40_RBBM_STATUS);
500 RREG32(R_0000F0_RBBM_SOFT_RESET);
504 status = RREG32(R_000E40_RBBM_STATUS);
569 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
664 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
666 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
670 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
708 RREG32(R_000040_GEN_INT_CNTL);
715 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
720 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
730 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
735 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
744 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
747 tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
762 u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
833 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
848 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
850 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
881 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
913 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
914 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
932 r = RREG32(R_000074_MC_IND_DATA);
1019 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1053 RREG32(R_000E40_RBBM_STATUS),
1054 RREG32(R_0007C0_CP_STAT));
1128 RREG32(R_000E40_RBBM_STATUS),
1129 RREG32(R_0007C0_CP_STAT));