Lines Matching refs:RREG32
65 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
75 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
76 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
99 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
124 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
145 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
161 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
239 tmp = RREG32(voltage->gpio.reg);
248 tmp = RREG32(voltage->gpio.reg);
334 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
352 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
367 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
372 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
390 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
398 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
469 status = RREG32(R_000E40_RBBM_STATUS);
475 status = RREG32(R_000E40_RBBM_STATUS);
479 tmp = RREG32(RADEON_CP_RB_CNTL);
491 RREG32(R_0000F0_RBBM_SOFT_RESET);
495 status = RREG32(R_000E40_RBBM_STATUS);
499 RREG32(R_0000F0_RBBM_SOFT_RESET);
503 status = RREG32(R_000E40_RBBM_STATUS);
507 RREG32(R_0000F0_RBBM_SOFT_RESET);
511 status = RREG32(R_000E40_RBBM_STATUS);
576 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
671 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
673 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
677 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
715 RREG32(R_000040_GEN_INT_CNTL);
722 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
727 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
737 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
742 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
751 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
754 tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
769 u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
840 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
855 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
857 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
888 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
920 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
921 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
939 r = RREG32(R_000074_MC_IND_DATA);
1020 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1054 RREG32(R_000E40_RBBM_STATUS),
1055 RREG32(R_0007C0_CP_STAT));
1129 RREG32(R_000E40_RBBM_STATUS),
1130 RREG32(R_0007C0_CP_STAT));