Lines Matching refs:RREG32
269 bus_cntl = RREG32(R600_BUS_CNTL);
270 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
271 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
272 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
273 rom_cntl = RREG32(R600_ROM_CNTL);
315 viph_control = RREG32(RADEON_VIPH_CONTROL);
316 bus_cntl = RREG32(R600_BUS_CNTL);
317 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
318 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
319 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
320 rom_cntl = RREG32(R600_ROM_CNTL);
337 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
346 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
361 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
388 viph_control = RREG32(RADEON_VIPH_CONTROL);
389 bus_cntl = RREG32(R600_BUS_CNTL);
390 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
391 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
392 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
393 rom_cntl = RREG32(R600_ROM_CNTL);
394 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
395 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
396 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
397 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
398 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
399 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
462 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
463 viph_control = RREG32(RADEON_VIPH_CONTROL);
464 bus_cntl = RREG32(RV370_BUS_CNTL);
465 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
466 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
467 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
468 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
469 gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
470 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
521 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
522 viph_control = RREG32(RADEON_VIPH_CONTROL);
524 bus_cntl = RREG32(RV370_BUS_CNTL);
526 bus_cntl = RREG32(RADEON_BUS_CNTL);
527 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
529 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
533 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
537 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);