Lines Matching refs:RREG32
200 RREG32(CG_SPLL_FUNC_CNTL);
202 RREG32(CG_SPLL_FUNC_CNTL_2);
204 RREG32(CG_SPLL_FUNC_CNTL_3);
206 RREG32(CG_SPLL_SPREAD_SPECTRUM);
208 RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
211 RREG32(TCI_MCLK_PWRMGT_CNTL);
213 RREG32(TCI_DLL_CNTL);
215 RREG32(CG_MPLL_FUNC_CNTL);
217 RREG32(CG_MPLL_FUNC_CNTL_2);
219 RREG32(CG_MPLL_FUNC_CNTL_3);
221 RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM);
223 RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM_2);
400 arb_refresh_rate = RREG32(MC_ARB_RFSH_RATE) &
409 old_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
410 old_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
416 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
417 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
426 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
427 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
436 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
437 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
479 mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0);
485 mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0);
500 mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0);
503 mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0);