| /kernel/linux/linux-6.6/include/asm-generic/ |
| H A D | percpu.h | 70 #define raw_cpu_generic_to_op(pcp, val, op) \
72 *raw_cpu_ptr(&(pcp)) op val; \
75 #define raw_cpu_generic_add_return(pcp, val) \
79 *__p += val; \
152 #define this_cpu_generic_to_op(pcp, val, op) \
156 raw_cpu_generic_to_op(pcp, val, op); \
161 #define this_cpu_generic_add_return(pcp, val) \
166 __ret = raw_cpu_generic_add_return(pcp, val); \
215 #define raw_cpu_write_1(pcp, val) raw_cpu_generic_to_op(pcp, val,
[all...] |
| /kernel/linux/linux-6.6/drivers/phy/socionext/ |
| H A D | phy-uniphier-ahci.c | 76 u32 val; in uniphier_ahciphy_pro4_init() local
79 val = readl(priv->base + CKCTRL0); in uniphier_ahciphy_pro4_init()
80 val &= ~CKCTRL0_NCY_MASK; in uniphier_ahciphy_pro4_init()
81 val |= FIELD_PREP(CKCTRL0_NCY_MASK, 0x6); in uniphier_ahciphy_pro4_init()
82 val &= ~CKCTRL0_NCY5_MASK; in uniphier_ahciphy_pro4_init()
83 val |= FIELD_PREP(CKCTRL0_NCY5_MASK, 0x2); in uniphier_ahciphy_pro4_init()
84 val &= ~CKCTRL0_PRESCALE_MASK; in uniphier_ahciphy_pro4_init()
85 val |= FIELD_PREP(CKCTRL0_PRESCALE_MASK, 0x1); in uniphier_ahciphy_pro4_init()
86 writel(val, priv->base + CKCTRL0); in uniphier_ahciphy_pro4_init()
89 val in uniphier_ahciphy_pro4_init()
114 u32 val; uniphier_ahciphy_pro4_power_on() local
177 u32 val; uniphier_ahciphy_pro4_power_off() local
199 u32 val; uniphier_ahciphy_pxs2_enable() local
219 u32 val; uniphier_ahciphy_pxs2_power_on() local
248 u32 val; uniphier_ahciphy_pxs3_init() local
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/ |
| H A D | intel_dram.c | 46 static int skl_get_dimm_size(u16 val) in skl_get_dimm_size() argument
48 return val & SKL_DRAM_SIZE_MASK; in skl_get_dimm_size()
51 static int skl_get_dimm_width(u16 val) in skl_get_dimm_width() argument
53 if (skl_get_dimm_size(val) == 0) in skl_get_dimm_width()
56 switch (val & SKL_DRAM_WIDTH_MASK) { in skl_get_dimm_width()
60 val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT; in skl_get_dimm_width()
61 return 8 << val; in skl_get_dimm_width()
63 MISSING_CASE(val); in skl_get_dimm_width()
68 static int skl_get_dimm_ranks(u16 val) in skl_get_dimm_ranks() argument
79 cnl_get_dimm_size(u16 val) cnl_get_dimm_size() argument
84 cnl_get_dimm_width(u16 val) cnl_get_dimm_width() argument
101 cnl_get_dimm_ranks(u16 val) cnl_get_dimm_ranks() argument
119 skl_dram_get_dimm_info(struct drm_i915_private *i915, struct dram_dimm_info *dimm, int channel, char dimm_name, u16 val) skl_dram_get_dimm_info() argument
140 skl_dram_get_channel_info(struct drm_i915_private *i915, struct dram_channel_info *ch, int channel, u32 val) skl_dram_get_channel_info() argument
184 u32 val; skl_dram_get_channels_info() local
232 u32 val; skl_get_dram_type() local
256 u32 mem_freq_khz, val; skl_get_dram_info() local
286 bxt_get_dimm_size(u32 val) bxt_get_dimm_size() argument
305 bxt_get_dimm_width(u32 val) bxt_get_dimm_width() argument
315 bxt_get_dimm_ranks(u32 val) bxt_get_dimm_ranks() argument
331 bxt_get_dimm_type(u32 val) bxt_get_dimm_type() argument
351 bxt_get_dimm_info(struct dram_dimm_info *dimm, u32 val) bxt_get_dimm_info() argument
367 u32 mem_freq_khz, val; bxt_get_dram_info() local
440 u32 val = 0; icl_pcode_read_mem_global_info() local
[all...] |
| /kernel/linux/linux-5.10/drivers/usb/phy/ |
| H A D | phy-tegra-usb.c | 206 u32 val; in set_pts() local
209 val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC); in set_pts()
210 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0); in set_pts()
211 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val); in set_pts()
212 writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC); in set_pts()
214 val = readl_relaxed(base + TEGRA_USB_PORTSC1); in set_pts()
215 val &= ~TEGRA_PORTSC1_RWC_BITS; in set_pts()
216 val &= ~TEGRA_USB_PORTSC1_PTS(~0); in set_pts()
217 val |= TEGRA_USB_PORTSC1_PTS(pts_val); in set_pts()
218 writel_relaxed(val, bas in set_pts()
225 u32 val; set_phcd() local
312 u32 val; utmip_pad_power_on() local
347 u32 val; utmip_pad_power_off() local
386 u32 val; utmi_phy_clk_disable() local
418 u32 val; utmi_phy_clk_enable() local
453 u32 val; utmi_phy_power_on() local
604 u32 val; utmi_phy_power_off() local
639 u32 val; utmi_phy_preresume() local
649 u32 val; utmi_phy_postresume() local
660 u32 val; utmi_phy_restore_start() local
680 u32 val; utmi_phy_restore_end() local
691 u32 val; ulpi_phy_power_on() local
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/adreno/ |
| H A D | a5xx.xml.h | 1043 static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) in A5XX_CP_PROTECT_REG_BASE_ADDR() argument
1045 return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK; in A5XX_CP_PROTECT_REG_BASE_ADDR()
1049 static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) in A5XX_CP_PROTECT_REG_MASK_LEN() argument
1051 return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK; in A5XX_CP_PROTECT_REG_MASK_LEN()
1055 static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val) in A5XX_CP_PROTECT_REG_TRAP_WRITE() argument
1057 return ((val) << A5XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK; in A5XX_CP_PROTECT_REG_TRAP_WRITE()
1061 static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_READ(uint32_t val) in A5XX_CP_PROTECT_REG_TRAP_READ() argument
1063 return ((val) << A5XX_CP_PROTECT_REG_TRAP_READ__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_READ__MASK; in A5XX_CP_PROTECT_REG_TRAP_READ()
1838 static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB(uint32_t val) in A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB() argument
1840 return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__SHIF in A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB()
1844 A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP(uint32_t val) A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP() argument
1850 A5XX_RBBM_STATUS_HLSQ_BUSY(uint32_t val) A5XX_RBBM_STATUS_HLSQ_BUSY() argument
1856 A5XX_RBBM_STATUS_VSC_BUSY(uint32_t val) A5XX_RBBM_STATUS_VSC_BUSY() argument
1862 A5XX_RBBM_STATUS_TPL1_BUSY(uint32_t val) A5XX_RBBM_STATUS_TPL1_BUSY() argument
1868 A5XX_RBBM_STATUS_SP_BUSY(uint32_t val) A5XX_RBBM_STATUS_SP_BUSY() argument
1874 A5XX_RBBM_STATUS_UCHE_BUSY(uint32_t val) A5XX_RBBM_STATUS_UCHE_BUSY() argument
1880 A5XX_RBBM_STATUS_VPC_BUSY(uint32_t val) A5XX_RBBM_STATUS_VPC_BUSY() argument
1886 A5XX_RBBM_STATUS_VFDP_BUSY(uint32_t val) A5XX_RBBM_STATUS_VFDP_BUSY() argument
1892 A5XX_RBBM_STATUS_VFD_BUSY(uint32_t val) A5XX_RBBM_STATUS_VFD_BUSY() argument
1898 A5XX_RBBM_STATUS_TESS_BUSY(uint32_t val) A5XX_RBBM_STATUS_TESS_BUSY() argument
1904 A5XX_RBBM_STATUS_PC_VSD_BUSY(uint32_t val) A5XX_RBBM_STATUS_PC_VSD_BUSY() argument
1910 A5XX_RBBM_STATUS_PC_DCALL_BUSY(uint32_t val) A5XX_RBBM_STATUS_PC_DCALL_BUSY() argument
1916 A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY(uint32_t val) A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY() argument
1922 A5XX_RBBM_STATUS_DCOM_BUSY(uint32_t val) A5XX_RBBM_STATUS_DCOM_BUSY() argument
1928 A5XX_RBBM_STATUS_COM_BUSY(uint32_t val) A5XX_RBBM_STATUS_COM_BUSY() argument
1934 A5XX_RBBM_STATUS_LRZ_BUZY(uint32_t val) A5XX_RBBM_STATUS_LRZ_BUZY() argument
1940 A5XX_RBBM_STATUS_A2D_DSP_BUSY(uint32_t val) A5XX_RBBM_STATUS_A2D_DSP_BUSY() argument
1946 A5XX_RBBM_STATUS_CCUFCHE_BUSY(uint32_t val) A5XX_RBBM_STATUS_CCUFCHE_BUSY() argument
1952 A5XX_RBBM_STATUS_RB_BUSY(uint32_t val) A5XX_RBBM_STATUS_RB_BUSY() argument
1958 A5XX_RBBM_STATUS_RAS_BUSY(uint32_t val) A5XX_RBBM_STATUS_RAS_BUSY() argument
1964 A5XX_RBBM_STATUS_TSE_BUSY(uint32_t val) A5XX_RBBM_STATUS_TSE_BUSY() argument
1970 A5XX_RBBM_STATUS_VBIF_BUSY(uint32_t val) A5XX_RBBM_STATUS_VBIF_BUSY() argument
1976 A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST(uint32_t val) A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST() argument
1982 A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST(uint32_t val) A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST() argument
1988 A5XX_RBBM_STATUS_CP_BUSY(uint32_t val) A5XX_RBBM_STATUS_CP_BUSY() argument
1994 A5XX_RBBM_STATUS_GPMU_MASTER_BUSY(uint32_t val) A5XX_RBBM_STATUS_GPMU_MASTER_BUSY() argument
2000 A5XX_RBBM_STATUS_CP_CRASH_BUSY(uint32_t val) A5XX_RBBM_STATUS_CP_CRASH_BUSY() argument
2006 A5XX_RBBM_STATUS_CP_ETS_BUSY(uint32_t val) A5XX_RBBM_STATUS_CP_ETS_BUSY() argument
2012 A5XX_RBBM_STATUS_CP_PFP_BUSY(uint32_t val) A5XX_RBBM_STATUS_CP_PFP_BUSY() argument
2018 A5XX_RBBM_STATUS_CP_ME_BUSY(uint32_t val) A5XX_RBBM_STATUS_CP_ME_BUSY() argument
2114 A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val) A5XX_VSC_BIN_SIZE_WIDTH() argument
2120 A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) A5XX_VSC_BIN_SIZE_HEIGHT() argument
2138 A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) A5XX_VSC_PIPE_CONFIG_REG_X() argument
2144 A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) A5XX_VSC_PIPE_CONFIG_REG_Y() argument
2150 A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) A5XX_VSC_PIPE_CONFIG_REG_W() argument
2156 A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) A5XX_VSC_PIPE_CONFIG_REG_H() argument
2179 A5XX_VSC_RESOLVE_CNTL_X(uint32_t val) A5XX_VSC_RESOLVE_CNTL_X() argument
2185 A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) A5XX_VSC_RESOLVE_CNTL_Y() argument
2817 A5XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val) A5XX_GRAS_VS_CL_CNTL_CLIP_MASK() argument
2823 A5XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val) A5XX_GRAS_VS_CL_CNTL_CULL_MASK() argument
2839 A5XX_GRAS_CNTL_COORD_MASK(uint32_t val) A5XX_GRAS_CNTL_COORD_MASK() argument
2847 A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ() argument
2853 A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT() argument
2861 A5XX_GRAS_CL_VPORT_XOFFSET_0(float val) A5XX_GRAS_CL_VPORT_XOFFSET_0() argument
2869 A5XX_GRAS_CL_VPORT_XSCALE_0(float val) A5XX_GRAS_CL_VPORT_XSCALE_0() argument
2877 A5XX_GRAS_CL_VPORT_YOFFSET_0(float val) A5XX_GRAS_CL_VPORT_YOFFSET_0() argument
2885 A5XX_GRAS_CL_VPORT_YSCALE_0(float val) A5XX_GRAS_CL_VPORT_YSCALE_0() argument
2893 A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val) A5XX_GRAS_CL_VPORT_ZOFFSET_0() argument
2901 A5XX_GRAS_CL_VPORT_ZSCALE_0(float val) A5XX_GRAS_CL_VPORT_ZSCALE_0() argument
2912 A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) A5XX_GRAS_SU_CNTL_LINEHALFWIDTH() argument
2919 A5XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val) A5XX_GRAS_SU_CNTL_LINE_MODE() argument
2927 A5XX_GRAS_SU_POINT_MINMAX_MIN(float val) A5XX_GRAS_SU_POINT_MINMAX_MIN() argument
2933 A5XX_GRAS_SU_POINT_MINMAX_MAX(float val) A5XX_GRAS_SU_POINT_MINMAX_MAX() argument
2941 A5XX_GRAS_SU_POINT_SIZE(float val) A5XX_GRAS_SU_POINT_SIZE() argument
2955 A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val) A5XX_GRAS_SU_POLY_OFFSET_SCALE() argument
2963 A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) A5XX_GRAS_SU_POLY_OFFSET_OFFSET() argument
2971 A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP() argument
2979 A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val) A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT() argument
2995 A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES() argument
3003 A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES() argument
3015 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val) A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X() argument
3021 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val) A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y() argument
3030 A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val) A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X() argument
3036 A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val) A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y() argument
3045 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val) A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X() argument
3051 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val) A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y() argument
3060 A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val) A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X() argument
3066 A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val) A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y() argument
3075 A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X() argument
3081 A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y() argument
3090 A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X() argument
3096 A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y() argument
3113 A5XX_GRAS_LRZ_BUFFER_PITCH(uint32_t val) A5XX_GRAS_LRZ_BUFFER_PITCH() argument
3125 A5XX_RB_CNTL_WIDTH(uint32_t val) A5XX_RB_CNTL_WIDTH() argument
3131 A5XX_RB_CNTL_HEIGHT(uint32_t val) A5XX_RB_CNTL_HEIGHT() argument
3145 A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) A5XX_RB_RENDER_CNTL_FLAG_MRTS() argument
3151 A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val) A5XX_RB_RENDER_CNTL_FLAG_MRTS2() argument
3159 A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) A5XX_RB_RAS_MSAA_CNTL_SAMPLES() argument
3167 A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) A5XX_RB_DEST_MSAA_CNTL_SAMPLES() argument
3182 A5XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val) A5XX_RB_RENDER_CONTROL0_COORD_MASK() argument
3195 A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val) A5XX_RB_FS_OUTPUT_CNTL_MRT() argument
3204 A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) A5XX_RB_RENDER_COMPONENTS_RT0() argument
3210 A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) A5XX_RB_RENDER_COMPONENTS_RT1() argument
3216 A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) A5XX_RB_RENDER_COMPONENTS_RT2() argument
3222 A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) A5XX_RB_RENDER_COMPONENTS_RT3() argument
3228 A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) A5XX_RB_RENDER_COMPONENTS_RT4() argument
3234 A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) A5XX_RB_RENDER_COMPONENTS_RT5() argument
3240 A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) A5XX_RB_RENDER_COMPONENTS_RT6() argument
3246 A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) A5XX_RB_RENDER_COMPONENTS_RT7() argument
3259 A5XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) A5XX_RB_MRT_CONTROL_ROP_CODE() argument
3265 A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE() argument
3273 A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR() argument
3279 A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE() argument
3285 A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR() argument
3291 A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR() argument
3297 A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE() argument
3303 A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR() argument
3311 A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT() argument
3317 A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val) A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE() argument
3323 A5XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) A5XX_RB_MRT_BUF_INFO_DITHER_MODE() argument
3329 A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) A5XX_RB_MRT_BUF_INFO_COLOR_SWAP() argument
3338 A5XX_RB_MRT_PITCH(uint32_t val) A5XX_RB_MRT_PITCH() argument
3346 A5XX_RB_MRT_ARRAY_PITCH(uint32_t val) A5XX_RB_MRT_ARRAY_PITCH() argument
3358 A5XX_RB_BLEND_RED_UINT(uint32_t val) A5XX_RB_BLEND_RED_UINT() argument
3364 A5XX_RB_BLEND_RED_SINT(uint32_t val) A5XX_RB_BLEND_RED_SINT() argument
3370 A5XX_RB_BLEND_RED_FLOAT(float val) A5XX_RB_BLEND_RED_FLOAT() argument
3378 A5XX_RB_BLEND_RED_F32(float val) A5XX_RB_BLEND_RED_F32() argument
3386 A5XX_RB_BLEND_GREEN_UINT(uint32_t val) A5XX_RB_BLEND_GREEN_UINT() argument
3392 A5XX_RB_BLEND_GREEN_SINT(uint32_t val) A5XX_RB_BLEND_GREEN_SINT() argument
3398 A5XX_RB_BLEND_GREEN_FLOAT(float val) A5XX_RB_BLEND_GREEN_FLOAT() argument
3406 A5XX_RB_BLEND_GREEN_F32(float val) A5XX_RB_BLEND_GREEN_F32() argument
3414 A5XX_RB_BLEND_BLUE_UINT(uint32_t val) A5XX_RB_BLEND_BLUE_UINT() argument
3420 A5XX_RB_BLEND_BLUE_SINT(uint32_t val) A5XX_RB_BLEND_BLUE_SINT() argument
3426 A5XX_RB_BLEND_BLUE_FLOAT(float val) A5XX_RB_BLEND_BLUE_FLOAT() argument
3434 A5XX_RB_BLEND_BLUE_F32(float val) A5XX_RB_BLEND_BLUE_F32() argument
3442 A5XX_RB_BLEND_ALPHA_UINT(uint32_t val) A5XX_RB_BLEND_ALPHA_UINT() argument
3448 A5XX_RB_BLEND_ALPHA_SINT(uint32_t val) A5XX_RB_BLEND_ALPHA_SINT() argument
3454 A5XX_RB_BLEND_ALPHA_FLOAT(float val) A5XX_RB_BLEND_ALPHA_FLOAT() argument
3462 A5XX_RB_BLEND_ALPHA_F32(float val) A5XX_RB_BLEND_ALPHA_F32() argument
3470 A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) A5XX_RB_ALPHA_CONTROL_ALPHA_REF() argument
3477 A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC() argument
3485 A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) A5XX_RB_BLEND_CNTL_ENABLE_BLEND() argument
3493 A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) A5XX_RB_BLEND_CNTL_SAMPLE_MASK() argument
3507 A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) A5XX_RB_DEPTH_CNTL_ZFUNC() argument
3516 A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val) A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT() argument
3528 A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) A5XX_RB_DEPTH_BUFFER_PITCH() argument
3536 A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH() argument
3547 A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) A5XX_RB_STENCIL_CONTROL_FUNC() argument
3553 A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) A5XX_RB_STENCIL_CONTROL_FAIL() argument
3559 A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) A5XX_RB_STENCIL_CONTROL_ZPASS() argument
3565 A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) A5XX_RB_STENCIL_CONTROL_ZFAIL() argument
3571 A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) A5XX_RB_STENCIL_CONTROL_FUNC_BF() argument
3577 A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) A5XX_RB_STENCIL_CONTROL_FAIL_BF() argument
3583 A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) A5XX_RB_STENCIL_CONTROL_ZPASS_BF() argument
3589 A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) A5XX_RB_STENCIL_CONTROL_ZFAIL_BF() argument
3604 A5XX_RB_STENCIL_PITCH(uint32_t val) A5XX_RB_STENCIL_PITCH() argument
3612 A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val) A5XX_RB_STENCIL_ARRAY_PITCH() argument
3620 A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) A5XX_RB_STENCILREFMASK_STENCILREF() argument
3626 A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) A5XX_RB_STENCILREFMASK_STENCILMASK() argument
3632 A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) A5XX_RB_STENCILREFMASK_STENCILWRITEMASK() argument
3640 A5XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) A5XX_RB_STENCILREFMASK_BF_STENCILREF() argument
3646 A5XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) A5XX_RB_STENCILREFMASK_BF_STENCILMASK() argument
3652 A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK() argument
3661 A5XX_RB_WINDOW_OFFSET_X(uint32_t val) A5XX_RB_WINDOW_OFFSET_X() argument
3667 A5XX_RB_WINDOW_OFFSET_Y(uint32_t val) A5XX_RB_WINDOW_OFFSET_Y() argument
3678 A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val) A5XX_RB_BLIT_CNTL_BUF() argument
3687 A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val) A5XX_RB_RESOLVE_CNTL_1_X() argument
3693 A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val) A5XX_RB_RESOLVE_CNTL_1_Y() argument
3702 A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val) A5XX_RB_RESOLVE_CNTL_2_X() argument
3708 A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val) A5XX_RB_RESOLVE_CNTL_2_Y() argument
3723 A5XX_RB_BLIT_DST_PITCH(uint32_t val) A5XX_RB_BLIT_DST_PITCH() argument
3731 A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) A5XX_RB_BLIT_DST_ARRAY_PITCH() argument
3749 A5XX_RB_CLEAR_CNTL_MASK(uint32_t val) A5XX_RB_CLEAR_CNTL_MASK() argument
3769 A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val) A5XX_RB_MRT_FLAG_BUFFER_PITCH() argument
3777 A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH() argument
3789 A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val) A5XX_RB_BLIT_FLAG_DST_PITCH() argument
3797 A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val) A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH() argument
3809 A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val) A5XX_VPC_CNTL_0_STRIDE_IN_VPC() argument
3836 A5XX_VPC_CLIP_CNTL_CLIP_MASK(uint32_t val) A5XX_VPC_CLIP_CNTL_CLIP_MASK() argument
3842 A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC() argument
3848 A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC() argument
3856 A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val) A5XX_VPC_PACK_NUMNONPOSVAR() argument
3862 A5XX_VPC_PACK_PSIZELOC(uint32_t val) A5XX_VPC_PACK_PSIZELOC() argument
3885 A5XX_VPC_SO_PROG_A_BUF(uint32_t val) A5XX_VPC_SO_PROG_A_BUF() argument
3891 A5XX_VPC_SO_PROG_A_OFF(uint32_t val) A5XX_VPC_SO_PROG_A_OFF() argument
3898 A5XX_VPC_SO_PROG_B_BUF(uint32_t val) A5XX_VPC_SO_PROG_B_BUF() argument
3904 A5XX_VPC_SO_PROG_B_OFF(uint32_t val) A5XX_VPC_SO_PROG_B_OFF() argument
3929 A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val) A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC() argument
3943 A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE() argument
3949 A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE() argument
3958 A5XX_PC_CLIP_CNTL_CLIP_MASK(uint32_t val) A5XX_PC_CLIP_CNTL_CLIP_MASK() argument
3970 A5XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val) A5XX_PC_GS_PARAM_MAX_VERTICES() argument
3976 A5XX_PC_GS_PARAM_INVOCATIONS(uint32_t val) A5XX_PC_GS_PARAM_INVOCATIONS() argument
3982 A5XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) A5XX_PC_GS_PARAM_PRIMTYPE() argument
3990 A5XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val) A5XX_PC_HS_PARAM_VERTICES_OUT() argument
3996 A5XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) A5XX_PC_HS_PARAM_SPACING() argument
4008 A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val) A5XX_VFD_CONTROL_0_VTXCNT() argument
4016 A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) A5XX_VFD_CONTROL_1_REGID4VTX() argument
4022 A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val) A5XX_VFD_CONTROL_1_REGID4INST() argument
4028 A5XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) A5XX_VFD_CONTROL_1_REGID4PRIMID() argument
4036 A5XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val) A5XX_VFD_CONTROL_2_REGID_PATCHID() argument
4044 A5XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val) A5XX_VFD_CONTROL_3_REGID_PATCHID() argument
4050 A5XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) A5XX_VFD_CONTROL_3_REGID_TESSX() argument
4056 A5XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) A5XX_VFD_CONTROL_3_REGID_TESSY() argument
4084 A5XX_VFD_DECODE_INSTR_IDX(uint32_t val) A5XX_VFD_DECODE_INSTR_IDX() argument
4091 A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val) A5XX_VFD_DECODE_INSTR_FORMAT() argument
4097 A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) A5XX_VFD_DECODE_INSTR_SWAP() argument
4111 A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK() argument
4117 A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) A5XX_VFD_DEST_CNTL_INSTR_REGID() argument
4130 A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET() argument
4136 A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(uint32_t val) A5XX_SP_VS_CONFIG_SHADEROBJOFFSET() argument
4145 A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET() argument
4151 A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(uint32_t val) A5XX_SP_FS_CONFIG_SHADEROBJOFFSET() argument
4160 A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET() argument
4166 A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(uint32_t val) A5XX_SP_HS_CONFIG_SHADEROBJOFFSET() argument
4175 A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET() argument
4181 A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(uint32_t val) A5XX_SP_DS_CONFIG_SHADEROBJOFFSET() argument
4190 A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET() argument
4196 A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(uint32_t val) A5XX_SP_GS_CONFIG_SHADEROBJOFFSET() argument
4205 A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET() argument
4211 A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(uint32_t val) A5XX_SP_CS_CONFIG_SHADEROBJOFFSET() argument
4224 A5XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) A5XX_SP_VS_CTRL_REG0_THREADSIZE() argument
4230 A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT() argument
4236 A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT() argument
4244 A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) A5XX_SP_VS_CTRL_REG0_BRANCHSTACK() argument
4252 A5XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val) A5XX_SP_PRIMITIVE_CNTL_VSOUT() argument
4262 A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val) A5XX_SP_VS_OUT_REG_A_REGID() argument
4268 A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) A5XX_SP_VS_OUT_REG_A_COMPMASK() argument
4274 A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val) A5XX_SP_VS_OUT_REG_B_REGID() argument
4280 A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) A5XX_SP_VS_OUT_REG_B_COMPMASK() argument
4290 A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) A5XX_SP_VS_VPC_DST_REG_OUTLOC0() argument
4296 A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) A5XX_SP_VS_VPC_DST_REG_OUTLOC1() argument
4302 A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) A5XX_SP_VS_VPC_DST_REG_OUTLOC2() argument
4308 A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) A5XX_SP_VS_VPC_DST_REG_OUTLOC3() argument
4323 A5XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) A5XX_SP_FS_CTRL_REG0_THREADSIZE() argument
4329 A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT() argument
4335 A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT() argument
4343 A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) A5XX_SP_FS_CTRL_REG0_BRANCHSTACK() argument
4357 A5XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val) A5XX_SP_BLEND_CNTL_ENABLE_BLEND() argument
4367 A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val) A5XX_SP_FS_OUTPUT_CNTL_MRT() argument
4373 A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val) A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID() argument
4379 A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val) A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID() argument
4389 A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) A5XX_SP_FS_OUTPUT_REG_REGID() argument
4400 A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val) A5XX_SP_FS_MRT_REG_COLOR_FORMAT() argument
4414 A5XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) A5XX_SP_CS_CTRL_REG0_THREADSIZE() argument
4420 A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT() argument
4426 A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT() argument
4434 A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) A5XX_SP_CS_CTRL_REG0_BRANCHSTACK() argument
4449 A5XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) A5XX_SP_HS_CTRL_REG0_THREADSIZE() argument
4455 A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT() argument
4461 A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT() argument
4469 A5XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) A5XX_SP_HS_CTRL_REG0_BRANCHSTACK() argument
4484 A5XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) A5XX_SP_DS_CTRL_REG0_THREADSIZE() argument
4490 A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT() argument
4496 A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT() argument
4504 A5XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) A5XX_SP_DS_CTRL_REG0_BRANCHSTACK() argument
4519 A5XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) A5XX_SP_GS_CTRL_REG0_THREADSIZE() argument
4525 A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT() argument
4531 A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT() argument
4539 A5XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) A5XX_SP_GS_CTRL_REG0_BRANCHSTACK() argument
4553 A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES() argument
4561 A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES() argument
4636 A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE() argument
4642 A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(enum a3xx_threadsize val) A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE() argument
4650 A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val) A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD() argument
4658 A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) A5XX_HLSQ_CONTROL_2_REG_FACEREGID() argument
4664 A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) A5XX_HLSQ_CONTROL_2_REG_SAMPLEID() argument
4670 A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK() argument
4676 A5XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val) A5XX_HLSQ_CONTROL_2_REG_CENTERRHW() argument
4684 A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL() argument
4690 A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL() argument
4696 A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID() argument
4702 A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID() argument
4710 A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val) A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE() argument
4716 A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val) A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE() argument
4722 A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID() argument
4728 A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID() argument
4739 A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET() argument
4745 A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(uint32_t val) A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET() argument
4754 A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET() argument
4760 A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(uint32_t val) A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET() argument
4769 A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET() argument
4775 A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(uint32_t val) A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET() argument
4784 A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET() argument
4790 A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(uint32_t val) A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET() argument
4799 A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET() argument
4805 A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(uint32_t val) A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET() argument
4814 A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET() argument
4820 A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(uint32_t val) A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET() argument
4829 A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val) A5XX_HLSQ_VS_CNTL_INSTRLEN() argument
4838 A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val) A5XX_HLSQ_FS_CNTL_INSTRLEN() argument
4847 A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val) A5XX_HLSQ_HS_CNTL_INSTRLEN() argument
4856 A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val) A5XX_HLSQ_DS_CNTL_INSTRLEN() argument
4865 A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val) A5XX_HLSQ_GS_CNTL_INSTRLEN() argument
4874 A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val) A5XX_HLSQ_CS_CNTL_INSTRLEN() argument
4888 A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM() argument
4894 A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX() argument
4900 A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY() argument
4906 A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ() argument
4914 A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X() argument
4922 A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X() argument
4930 A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y() argument
4938 A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y() argument
4946 A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z() argument
4954 A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z() argument
4962 A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID() argument
4968 A5XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val) A5XX_HLSQ_CS_CNTL_0_UNK0() argument
4974 A5XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val) A5XX_HLSQ_CS_CNTL_0_UNK1() argument
4980 A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID() argument
5036 A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) A5XX_RB_2D_SRC_INFO_COLOR_FORMAT() argument
5042 A5XX_RB_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val) A5XX_RB_2D_SRC_INFO_TILE_MODE() argument
5048 A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) A5XX_RB_2D_SRC_INFO_COLOR_SWAP() argument
5062 A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val) A5XX_RB_2D_SRC_SIZE_PITCH() argument
5068 A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val) A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH() argument
5076 A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) A5XX_RB_2D_DST_INFO_COLOR_FORMAT() argument
5082 A5XX_RB_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val) A5XX_RB_2D_DST_INFO_TILE_MODE() argument
5088 A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) A5XX_RB_2D_DST_INFO_COLOR_SWAP() argument
5102 A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val) A5XX_RB_2D_DST_SIZE_PITCH() argument
5108 A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val) A5XX_RB_2D_DST_SIZE_ARRAY_PITCH() argument
5120 A5XX_RB_2D_SRC_FLAGS_PITCH(uint32_t val) A5XX_RB_2D_SRC_FLAGS_PITCH() argument
5132 A5XX_RB_2D_DST_FLAGS_PITCH(uint32_t val) A5XX_RB_2D_DST_FLAGS_PITCH() argument
5142 A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT() argument
5148 A5XX_GRAS_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val) A5XX_GRAS_2D_SRC_INFO_TILE_MODE() argument
5154 A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP() argument
5164 A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT() argument
5170 A5XX_GRAS_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val) A5XX_GRAS_2D_DST_INFO_TILE_MODE() argument
5176 A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) A5XX_GRAS_2D_DST_INFO_COLOR_SWAP() argument
5189 A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val) A5XX_TEX_SAMP_0_XY_MAG() argument
5195 A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val) A5XX_TEX_SAMP_0_XY_MIN() argument
5201 A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val) A5XX_TEX_SAMP_0_WRAP_S() argument
5207 A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val) A5XX_TEX_SAMP_0_WRAP_T() argument
5213 A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val) A5XX_TEX_SAMP_0_WRAP_R() argument
5219 A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val) A5XX_TEX_SAMP_0_ANISO() argument
5225 A5XX_TEX_SAMP_0_LOD_BIAS(float val) A5XX_TEX_SAMP_0_LOD_BIAS() argument
5233 A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) A5XX_TEX_SAMP_1_COMPARE_FUNC() argument
5242 A5XX_TEX_SAMP_1_MAX_LOD(float val) A5XX_TEX_SAMP_1_MAX_LOD() argument
5248 A5XX_TEX_SAMP_1_MIN_LOD(float val) A5XX_TEX_SAMP_1_MIN_LOD() argument
5256 A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val) A5XX_TEX_SAMP_2_BCOLOR_OFFSET() argument
5266 A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val) A5XX_TEX_CONST_0_TILE_MODE() argument
5273 A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val) A5XX_TEX_CONST_0_SWIZ_X() argument
5279 A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val) A5XX_TEX_CONST_0_SWIZ_Y() argument
5285 A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val) A5XX_TEX_CONST_0_SWIZ_Z() argument
5291 A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val) A5XX_TEX_CONST_0_SWIZ_W() argument
5297 A5XX_TEX_CONST_0_MIPLVLS(uint32_t val) A5XX_TEX_CONST_0_MIPLVLS() argument
5303 A5XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val) A5XX_TEX_CONST_0_SAMPLES() argument
5309 A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val) A5XX_TEX_CONST_0_FMT() argument
5315 A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) A5XX_TEX_CONST_0_SWAP() argument
5323 A5XX_TEX_CONST_1_WIDTH(uint32_t val) A5XX_TEX_CONST_1_WIDTH() argument
5329 A5XX_TEX_CONST_1_HEIGHT(uint32_t val) A5XX_TEX_CONST_1_HEIGHT() argument
5338 A5XX_TEX_CONST_2_PITCHALIGN(uint32_t val) A5XX_TEX_CONST_2_PITCHALIGN() argument
5344 A5XX_TEX_CONST_2_PITCH(uint32_t val) A5XX_TEX_CONST_2_PITCH() argument
5350 A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val) A5XX_TEX_CONST_2_TYPE() argument
5358 A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) A5XX_TEX_CONST_3_ARRAY_PITCH() argument
5364 A5XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val) A5XX_TEX_CONST_3_MIN_LAYERSZ() argument
5374 A5XX_TEX_CONST_4_BASE_LO(uint32_t val) A5XX_TEX_CONST_4_BASE_LO() argument
5382 A5XX_TEX_CONST_5_BASE_HI(uint32_t val) A5XX_TEX_CONST_5_BASE_HI() argument
5388 A5XX_TEX_CONST_5_DEPTH(uint32_t val) A5XX_TEX_CONST_5_DEPTH() argument
5408 A5XX_SSBO_0_0_BASE_LO(uint32_t val) A5XX_SSBO_0_0_BASE_LO() argument
5416 A5XX_SSBO_0_1_PITCH(uint32_t val) A5XX_SSBO_0_1_PITCH() argument
5424 A5XX_SSBO_0_2_ARRAY_PITCH(uint32_t val) A5XX_SSBO_0_2_ARRAY_PITCH() argument
5432 A5XX_SSBO_0_3_CPP(uint32_t val) A5XX_SSBO_0_3_CPP() argument
5440 A5XX_SSBO_1_0_FMT(enum a5xx_tex_fmt val) A5XX_SSBO_1_0_FMT() argument
5446 A5XX_SSBO_1_0_WIDTH(uint32_t val) A5XX_SSBO_1_0_WIDTH() argument
5454 A5XX_SSBO_1_1_HEIGHT(uint32_t val) A5XX_SSBO_1_1_HEIGHT() argument
5460 A5XX_SSBO_1_1_DEPTH(uint32_t val) A5XX_SSBO_1_1_DEPTH() argument
5468 A5XX_SSBO_2_0_BASE_LO(uint32_t val) A5XX_SSBO_2_0_BASE_LO() argument
5476 A5XX_SSBO_2_1_BASE_HI(uint32_t val) A5XX_SSBO_2_1_BASE_HI() argument
5484 A5XX_UBO_0_BASE_LO(uint32_t val) A5XX_UBO_0_BASE_LO() argument
5492 A5XX_UBO_1_BASE_HI(uint32_t val) A5XX_UBO_1_BASE_HI() argument
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp4/ |
| H A D | mdp4.xml.h | 113 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val) in MDP4_VERSION_MINOR() argument
115 return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK; in MDP4_VERSION_MINOR()
119 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val) in MDP4_VERSION_MAJOR() argument
121 return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK; in MDP4_VERSION_MAJOR()
141 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_PRIM() argument
143 return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK; in MDP4_DISP_INTF_SEL_PRIM()
147 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_SEC() argument
149 return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK; in MDP4_DISP_INTF_SEL_SEC()
153 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_EXT() argument
155 return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIF in MDP4_DISP_INTF_SEL_EXT()
183 MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER2_IN_CFG_PIPE0() argument
190 MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER2_IN_CFG_PIPE1() argument
197 MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER2_IN_CFG_PIPE2() argument
204 MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER2_IN_CFG_PIPE3() argument
211 MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER2_IN_CFG_PIPE4() argument
218 MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER2_IN_CFG_PIPE5() argument
225 MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER2_IN_CFG_PIPE6() argument
232 MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER2_IN_CFG_PIPE7() argument
243 MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER_IN_CFG_PIPE0() argument
250 MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER_IN_CFG_PIPE1() argument
257 MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER_IN_CFG_PIPE2() argument
264 MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER_IN_CFG_PIPE3() argument
271 MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER_IN_CFG_PIPE4() argument
278 MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER_IN_CFG_PIPE5() argument
285 MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER_IN_CFG_PIPE6() argument
292 MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER_IN_CFG_PIPE7() argument
326 MDP4_OVLP_SIZE_HEIGHT(uint32_t val) MDP4_OVLP_SIZE_HEIGHT() argument
332 MDP4_OVLP_SIZE_WIDTH(uint32_t val) MDP4_OVLP_SIZE_WIDTH() argument
358 MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val) MDP4_OVLP_STAGE_OP_FG_ALPHA() argument
366 MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val) MDP4_OVLP_STAGE_OP_BG_ALPHA() argument
461 MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val) MDP4_DMA_CONFIG_G_BPC() argument
467 MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val) MDP4_DMA_CONFIG_B_BPC() argument
473 MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val) MDP4_DMA_CONFIG_R_BPC() argument
480 MDP4_DMA_CONFIG_PACK(uint32_t val) MDP4_DMA_CONFIG_PACK() argument
490 MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val) MDP4_DMA_SRC_SIZE_HEIGHT() argument
496 MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val) MDP4_DMA_SRC_SIZE_WIDTH() argument
508 MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val) MDP4_DMA_DST_SIZE_HEIGHT() argument
514 MDP4_DMA_DST_SIZE_WIDTH(uint32_t val) MDP4_DMA_DST_SIZE_WIDTH() argument
522 MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val) MDP4_DMA_CURSOR_SIZE_WIDTH() argument
528 MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val) MDP4_DMA_CURSOR_SIZE_HEIGHT() argument
538 MDP4_DMA_CURSOR_POS_X(uint32_t val) MDP4_DMA_CURSOR_POS_X() argument
544 MDP4_DMA_CURSOR_POS_Y(uint32_t val) MDP4_DMA_CURSOR_POS_Y() argument
553 MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val) MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT() argument
595 MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val) MDP4_PIPE_SRC_SIZE_HEIGHT() argument
601 MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val) MDP4_PIPE_SRC_SIZE_WIDTH() argument
609 MDP4_PIPE_SRC_XY_Y(uint32_t val) MDP4_PIPE_SRC_XY_Y() argument
615 MDP4_PIPE_SRC_XY_X(uint32_t val) MDP4_PIPE_SRC_XY_X() argument
623 MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val) MDP4_PIPE_DST_SIZE_HEIGHT() argument
629 MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val) MDP4_PIPE_DST_SIZE_WIDTH() argument
637 MDP4_PIPE_DST_XY_Y(uint32_t val) MDP4_PIPE_DST_XY_Y() argument
643 MDP4_PIPE_DST_XY_X(uint32_t val) MDP4_PIPE_DST_XY_X() argument
659 MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val) MDP4_PIPE_SRC_STRIDE_A_P0() argument
665 MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val) MDP4_PIPE_SRC_STRIDE_A_P1() argument
673 MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val) MDP4_PIPE_SRC_STRIDE_B_P2() argument
679 MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val) MDP4_PIPE_SRC_STRIDE_B_P3() argument
687 MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val) MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT() argument
693 MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val) MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH() argument
701 MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val) MDP4_PIPE_SRC_FORMAT_G_BPC() argument
707 MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val) MDP4_PIPE_SRC_FORMAT_B_BPC() argument
713 MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val) MDP4_PIPE_SRC_FORMAT_R_BPC() argument
719 MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val) MDP4_PIPE_SRC_FORMAT_A_BPC() argument
726 MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val) MDP4_PIPE_SRC_FORMAT_CPP() argument
733 MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val) MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT() argument
741 MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val) MDP4_PIPE_SRC_FORMAT_FETCH_PLANES() argument
748 MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val) MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP() argument
754 MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val) MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT() argument
762 MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val) MDP4_PIPE_SRC_UNPACK_ELEM0() argument
768 MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val) MDP4_PIPE_SRC_UNPACK_ELEM1() argument
774 MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val) MDP4_PIPE_SRC_UNPACK_ELEM2() argument
780 MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val) MDP4_PIPE_SRC_UNPACK_ELEM3() argument
790 MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val) MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL() argument
796 MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val) MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL() argument
848 MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val) MDP4_LCDC_HSYNC_CTRL_PULSEW() argument
854 MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val) MDP4_LCDC_HSYNC_CTRL_PERIOD() argument
866 MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val) MDP4_LCDC_DISPLAY_HCTRL_START() argument
872 MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val) MDP4_LCDC_DISPLAY_HCTRL_END() argument
884 MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val) MDP4_LCDC_ACTIVE_HCTL_START() argument
890 MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val) MDP4_LCDC_ACTIVE_HCTL_END() argument
905 MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val) MDP4_LCDC_UNDERFLOW_CLR_COLOR() argument
943 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val) MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0() argument
949 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val) MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1() argument
955 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val) MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2() argument
961 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val) MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3() argument
969 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val) MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4() argument
975 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val) MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5() argument
981 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val) MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6() argument
1022 MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val) MDP4_DTV_HSYNC_CTRL_PULSEW() argument
1028 MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val) MDP4_DTV_HSYNC_CTRL_PERIOD() argument
1040 MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val) MDP4_DTV_DISPLAY_HCTRL_START() argument
1046 MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val) MDP4_DTV_DISPLAY_HCTRL_END() argument
1058 MDP4_DTV_ACTIVE_HCTL_START(uint32_t val) MDP4_DTV_ACTIVE_HCTL_START() argument
1064 MDP4_DTV_ACTIVE_HCTL_END(uint32_t val) MDP4_DTV_ACTIVE_HCTL_END() argument
1079 MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val) MDP4_DTV_UNDERFLOW_CLR_COLOR() argument
1101 MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val) MDP4_DSI_HSYNC_CTRL_PULSEW() argument
1107 MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val) MDP4_DSI_HSYNC_CTRL_PERIOD() argument
1119 MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val) MDP4_DSI_DISPLAY_HCTRL_START() argument
1125 MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val) MDP4_DSI_DISPLAY_HCTRL_END() argument
1137 MDP4_DSI_ACTIVE_HCTL_START(uint32_t val) MDP4_DSI_ACTIVE_HCTL_START() argument
1143 MDP4_DSI_ACTIVE_HCTL_END(uint32_t val) MDP4_DSI_ACTIVE_HCTL_END() argument
1158 MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val) MDP4_DSI_UNDERFLOW_CLR_COLOR() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/mdp4/ |
| H A D | mdp4.xml.h | 120 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val) in MDP4_VERSION_MINOR() argument
122 return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK; in MDP4_VERSION_MINOR()
126 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val) in MDP4_VERSION_MAJOR() argument
128 return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK; in MDP4_VERSION_MAJOR()
148 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_PRIM() argument
150 return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK; in MDP4_DISP_INTF_SEL_PRIM()
154 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_SEC() argument
156 return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK; in MDP4_DISP_INTF_SEL_SEC()
160 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_EXT() argument
162 return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIF in MDP4_DISP_INTF_SEL_EXT()
190 MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER2_IN_CFG_PIPE0() argument
197 MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER2_IN_CFG_PIPE1() argument
204 MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER2_IN_CFG_PIPE2() argument
211 MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER2_IN_CFG_PIPE3() argument
218 MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER2_IN_CFG_PIPE4() argument
225 MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER2_IN_CFG_PIPE5() argument
232 MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER2_IN_CFG_PIPE6() argument
239 MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER2_IN_CFG_PIPE7() argument
250 MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER_IN_CFG_PIPE0() argument
257 MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER_IN_CFG_PIPE1() argument
264 MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER_IN_CFG_PIPE2() argument
271 MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER_IN_CFG_PIPE3() argument
278 MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER_IN_CFG_PIPE4() argument
285 MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER_IN_CFG_PIPE5() argument
292 MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER_IN_CFG_PIPE6() argument
299 MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val) MDP4_LAYERMIXER_IN_CFG_PIPE7() argument
333 MDP4_OVLP_SIZE_HEIGHT(uint32_t val) MDP4_OVLP_SIZE_HEIGHT() argument
339 MDP4_OVLP_SIZE_WIDTH(uint32_t val) MDP4_OVLP_SIZE_WIDTH() argument
365 MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val) MDP4_OVLP_STAGE_OP_FG_ALPHA() argument
373 MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val) MDP4_OVLP_STAGE_OP_BG_ALPHA() argument
468 MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val) MDP4_DMA_CONFIG_G_BPC() argument
474 MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val) MDP4_DMA_CONFIG_B_BPC() argument
480 MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val) MDP4_DMA_CONFIG_R_BPC() argument
487 MDP4_DMA_CONFIG_PACK(uint32_t val) MDP4_DMA_CONFIG_PACK() argument
497 MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val) MDP4_DMA_SRC_SIZE_HEIGHT() argument
503 MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val) MDP4_DMA_SRC_SIZE_WIDTH() argument
515 MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val) MDP4_DMA_DST_SIZE_HEIGHT() argument
521 MDP4_DMA_DST_SIZE_WIDTH(uint32_t val) MDP4_DMA_DST_SIZE_WIDTH() argument
529 MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val) MDP4_DMA_CURSOR_SIZE_WIDTH() argument
535 MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val) MDP4_DMA_CURSOR_SIZE_HEIGHT() argument
545 MDP4_DMA_CURSOR_POS_X(uint32_t val) MDP4_DMA_CURSOR_POS_X() argument
551 MDP4_DMA_CURSOR_POS_Y(uint32_t val) MDP4_DMA_CURSOR_POS_Y() argument
560 MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val) MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT() argument
602 MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val) MDP4_PIPE_SRC_SIZE_HEIGHT() argument
608 MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val) MDP4_PIPE_SRC_SIZE_WIDTH() argument
616 MDP4_PIPE_SRC_XY_Y(uint32_t val) MDP4_PIPE_SRC_XY_Y() argument
622 MDP4_PIPE_SRC_XY_X(uint32_t val) MDP4_PIPE_SRC_XY_X() argument
630 MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val) MDP4_PIPE_DST_SIZE_HEIGHT() argument
636 MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val) MDP4_PIPE_DST_SIZE_WIDTH() argument
644 MDP4_PIPE_DST_XY_Y(uint32_t val) MDP4_PIPE_DST_XY_Y() argument
650 MDP4_PIPE_DST_XY_X(uint32_t val) MDP4_PIPE_DST_XY_X() argument
666 MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val) MDP4_PIPE_SRC_STRIDE_A_P0() argument
672 MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val) MDP4_PIPE_SRC_STRIDE_A_P1() argument
680 MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val) MDP4_PIPE_SRC_STRIDE_B_P2() argument
686 MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val) MDP4_PIPE_SRC_STRIDE_B_P3() argument
694 MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val) MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT() argument
700 MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val) MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH() argument
708 MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val) MDP4_PIPE_SRC_FORMAT_G_BPC() argument
714 MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val) MDP4_PIPE_SRC_FORMAT_B_BPC() argument
720 MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val) MDP4_PIPE_SRC_FORMAT_R_BPC() argument
726 MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val) MDP4_PIPE_SRC_FORMAT_A_BPC() argument
733 MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val) MDP4_PIPE_SRC_FORMAT_CPP() argument
740 MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val) MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT() argument
748 MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val) MDP4_PIPE_SRC_FORMAT_FETCH_PLANES() argument
755 MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val) MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP() argument
761 MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val) MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT() argument
769 MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val) MDP4_PIPE_SRC_UNPACK_ELEM0() argument
775 MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val) MDP4_PIPE_SRC_UNPACK_ELEM1() argument
781 MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val) MDP4_PIPE_SRC_UNPACK_ELEM2() argument
787 MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val) MDP4_PIPE_SRC_UNPACK_ELEM3() argument
797 MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val) MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL() argument
803 MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val) MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL() argument
855 MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val) MDP4_LCDC_HSYNC_CTRL_PULSEW() argument
861 MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val) MDP4_LCDC_HSYNC_CTRL_PERIOD() argument
873 MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val) MDP4_LCDC_DISPLAY_HCTRL_START() argument
879 MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val) MDP4_LCDC_DISPLAY_HCTRL_END() argument
891 MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val) MDP4_LCDC_ACTIVE_HCTL_START() argument
897 MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val) MDP4_LCDC_ACTIVE_HCTL_END() argument
912 MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val) MDP4_LCDC_UNDERFLOW_CLR_COLOR() argument
950 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val) MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0() argument
956 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val) MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1() argument
962 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val) MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2() argument
968 MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val) MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3() argument
976 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val) MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4() argument
982 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val) MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5() argument
988 MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val) MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6() argument
1029 MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val) MDP4_DTV_HSYNC_CTRL_PULSEW() argument
1035 MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val) MDP4_DTV_HSYNC_CTRL_PERIOD() argument
1047 MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val) MDP4_DTV_DISPLAY_HCTRL_START() argument
1053 MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val) MDP4_DTV_DISPLAY_HCTRL_END() argument
1065 MDP4_DTV_ACTIVE_HCTL_START(uint32_t val) MDP4_DTV_ACTIVE_HCTL_START() argument
1071 MDP4_DTV_ACTIVE_HCTL_END(uint32_t val) MDP4_DTV_ACTIVE_HCTL_END() argument
1086 MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val) MDP4_DTV_UNDERFLOW_CLR_COLOR() argument
1108 MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val) MDP4_DSI_HSYNC_CTRL_PULSEW() argument
1114 MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val) MDP4_DSI_HSYNC_CTRL_PERIOD() argument
1126 MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val) MDP4_DSI_DISPLAY_HCTRL_START() argument
1132 MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val) MDP4_DSI_DISPLAY_HCTRL_END() argument
1144 MDP4_DSI_ACTIVE_HCTL_START(uint32_t val) MDP4_DSI_ACTIVE_HCTL_START() argument
1150 MDP4_DSI_ACTIVE_HCTL_END(uint32_t val) MDP4_DSI_ACTIVE_HCTL_END() argument
1165 MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val) MDP4_DSI_UNDERFLOW_CLR_COLOR() argument
[all...] |
| /kernel/linux/linux-5.10/arch/x86/include/asm/ |
| H A D | percpu.h | 76 #define __pcpu_cast_1(val) ((u8)(((unsigned long) val) & 0xff))
77 #define __pcpu_cast_2(val) ((u16)(((unsigned long) val) & 0xffff))
78 #define __pcpu_cast_4(val) ((u32)(((unsigned long) val) & 0xffffffff))
79 #define __pcpu_cast_8(val) ((u64)(val))
109 asm qual(__pcpu_op2_##size(op, "%[val]", __percpu_arg([var])) \
111 : [val] __pcpu_reg_imm
[all...] |
| /kernel/linux/linux-6.6/arch/x86/include/asm/ |
| H A D | percpu.h | 76 #define __pcpu_cast_1(val) ((u8)(((unsigned long) val) & 0xff))
77 #define __pcpu_cast_2(val) ((u16)(((unsigned long) val) & 0xffff))
78 #define __pcpu_cast_4(val) ((u32)(((unsigned long) val) & 0xffffffff))
79 #define __pcpu_cast_8(val) ((u64)(val))
109 asm qual(__pcpu_op2_##size(op, "%[val]", __percpu_arg([var])) \
111 : [val] __pcpu_reg_imm
[all...] |
| /kernel/linux/linux-6.6/drivers/power/supply/ |
| H A D | adp5061.c | 145 static int adp5061_get_array_index(const int *array, u8 size, int val) in adp5061_get_array_index() argument
150 if (val < array[i]) in adp5061_get_array_index()
176 union power_supply_propval *val) in adp5061_get_input_current_limit()
186 val->intval = adp5061_in_current_lim[mode] * 1000; in adp5061_get_input_current_limit()
191 static int adp5061_set_input_current_limit(struct adp5061_state *st, int val) in adp5061_set_input_current_limit() argument
196 val /= 1000; in adp5061_set_input_current_limit()
199 val); in adp5061_set_input_current_limit()
208 static int adp5061_set_min_voltage(struct adp5061_state *st, int val) in adp5061_set_min_voltage() argument
213 val /= 1000; in adp5061_set_min_voltage()
216 val); in adp5061_set_min_voltage()
175 adp5061_get_input_current_limit(struct adp5061_state *st, union power_supply_propval *val) adp5061_get_input_current_limit() argument
225 adp5061_get_min_voltage(struct adp5061_state *st, union power_supply_propval *val) adp5061_get_min_voltage() argument
241 adp5061_get_chg_volt_lim(struct adp5061_state *st, union power_supply_propval *val) adp5061_get_chg_volt_lim() argument
257 adp5061_get_max_voltage(struct adp5061_state *st, union power_supply_propval *val) adp5061_get_max_voltage() argument
276 adp5061_set_max_voltage(struct adp5061_state *st, int val) adp5061_set_max_voltage() argument
297 adp5061_set_const_chg_vmax(struct adp5061_state *st, int val) adp5061_set_const_chg_vmax() argument
314 adp5061_set_const_chg_current(struct adp5061_state *st, int val) adp5061_set_const_chg_current() argument
335 adp5061_get_const_chg_current(struct adp5061_state *st, union power_supply_propval *val) adp5061_get_const_chg_current() argument
354 adp5061_get_prechg_current(struct adp5061_state *st, union power_supply_propval *val) adp5061_get_prechg_current() argument
370 adp5061_set_prechg_current(struct adp5061_state *st, int val) adp5061_set_prechg_current() argument
387 adp5061_get_vweak_th(struct adp5061_state *st, union power_supply_propval *val) adp5061_get_vweak_th() argument
403 adp5061_set_vweak_th(struct adp5061_state *st, int val) adp5061_set_vweak_th() argument
420 adp5061_get_chg_type(struct adp5061_state *st, union power_supply_propval *val) adp5061_get_chg_type() argument
439 adp5061_get_charger_status(struct adp5061_state *st, union power_supply_propval *val) adp5061_get_charger_status() argument
472 adp5061_get_battery_status(struct adp5061_state *st, union power_supply_propval *val) adp5061_get_battery_status() argument
504 adp5061_get_termination_current(struct adp5061_state *st, union power_supply_propval *val) adp5061_get_termination_current() argument
520 adp5061_set_termination_current(struct adp5061_state *st, int val) adp5061_set_termination_current() argument
535 adp5061_get_property(struct power_supply *psy, enum power_supply_property psp, union power_supply_propval *val) adp5061_get_property() argument
619 adp5061_set_property(struct power_supply *psy, enum power_supply_property psp, const union power_supply_propval *val) adp5061_set_property() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/media/platform/qcom/camss/ |
| H A D | camss-csid-gen2.c | 340 u32 val; in __csid_configure_stream() local
371 val = vc << TPG_VC_CFG0_VC_NUM; in __csid_configure_stream()
372 val |= INTELEAVING_MODE_ONE_SHOT << TPG_VC_CFG0_LINE_INTERLEAVING_MODE; in __csid_configure_stream()
373 val |= 0 << TPG_VC_CFG0_NUM_FRAMES; in __csid_configure_stream()
374 writel_relaxed(val, csid->base + CSID_TPG_VC_CFG0); in __csid_configure_stream()
376 val = 0x740 << TPG_VC_CFG1_H_BLANKING_COUNT; in __csid_configure_stream()
377 val |= 0x3ff << TPG_VC_CFG1_V_BLANKING_COUNT; in __csid_configure_stream()
378 writel_relaxed(val, csid->base + CSID_TPG_VC_CFG1); in __csid_configure_stream()
382 val = (input_format->height & 0x1fff) << TPG_DT_n_CFG_0_FRAME_HEIGHT; in __csid_configure_stream()
383 val | in __csid_configure_stream()
482 csid_configure_testgen_pattern(struct csid_device *csid, s32 val) csid_configure_testgen_pattern() argument
523 u32 val; csid_isr() local
559 u32 val; csid_reset() local
[all...] |
| /kernel/linux/linux-6.6/drivers/media/platform/nxp/imx8-isi/ |
| H A D | imx8-isi-hw.c | 21 static inline void mxc_isi_write(struct mxc_isi_pipe *pipe, u32 reg, u32 val) in mxc_isi_write() argument
23 writel(val, pipe->regs + reg); in mxc_isi_write()
42 int val; in mxc_isi_channel_set_outbuf() local
44 val = mxc_isi_read(pipe, CHNL_OUT_BUF_CTRL); in mxc_isi_channel_set_outbuf()
61 val ^= CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR; in mxc_isi_channel_set_outbuf()
77 val ^= CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR; in mxc_isi_channel_set_outbuf()
80 mxc_isi_write(pipe, CHNL_OUT_BUF_CTRL, val); in mxc_isi_channel_set_outbuf()
85 u32 val; in mxc_isi_channel_m2m_start() local
87 val = mxc_isi_read(pipe, CHNL_MEM_RD_CTRL); in mxc_isi_channel_m2m_start()
88 val in mxc_isi_channel_m2m_start()
126 u32 val; mxc_isi_channel_set_scaling() local
173 u32 val, val0, val1; mxc_isi_channel_set_crop() local
220 u32 val; mxc_isi_channel_set_csc() local
261 u32 val; mxc_isi_channel_set_alpha() local
272 u32 val; mxc_isi_channel_set_flip() local
288 u32 val; mxc_isi_channel_set_panic_threshold() local
308 u32 val; mxc_isi_channel_set_control() local
400 u32 val; mxc_isi_channel_set_output_format() local
438 u32 val; mxc_isi_channel_irq_enable() local
508 u32 val; mxc_isi_channel_enable() local
523 u32 val; mxc_isi_channel_disable() local
[all...] |
| /kernel/linux/linux-5.10/include/sound/ |
| H A D | emu8000_reg.h | 108 #define EMU8000_CPF_WRITE(emu, chan, val) \
109 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(0, (chan)), (val))
110 #define EMU8000_PTRX_WRITE(emu, chan, val) \
111 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(1, (chan)), (val))
112 #define EMU8000_CVCF_WRITE(emu, chan, val) \
113 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(2, (chan)), (val))
114 #define EMU8000_VTFT_WRITE(emu, chan, val) \
115 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(3, (chan)), (val))
116 #define EMU8000_PSST_WRITE(emu, chan, val) \
117 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(6, (chan)), (val))
[all...] |
| /kernel/linux/linux-5.10/drivers/power/supply/ |
| H A D | adp5061.c | 145 static int adp5061_get_array_index(const int *array, u8 size, int val) in adp5061_get_array_index() argument
150 if (val < array[i]) in adp5061_get_array_index()
176 union power_supply_propval *val) in adp5061_get_input_current_limit()
186 val->intval = adp5061_in_current_lim[mode] * 1000; in adp5061_get_input_current_limit()
191 static int adp5061_set_input_current_limit(struct adp5061_state *st, int val) in adp5061_set_input_current_limit() argument
196 val /= 1000; in adp5061_set_input_current_limit()
199 val); in adp5061_set_input_current_limit()
208 static int adp5061_set_min_voltage(struct adp5061_state *st, int val) in adp5061_set_min_voltage() argument
213 val /= 1000; in adp5061_set_min_voltage()
216 val); in adp5061_set_min_voltage()
175 adp5061_get_input_current_limit(struct adp5061_state *st, union power_supply_propval *val) adp5061_get_input_current_limit() argument
225 adp5061_get_min_voltage(struct adp5061_state *st, union power_supply_propval *val) adp5061_get_min_voltage() argument
241 adp5061_get_chg_volt_lim(struct adp5061_state *st, union power_supply_propval *val) adp5061_get_chg_volt_lim() argument
257 adp5061_get_max_voltage(struct adp5061_state *st, union power_supply_propval *val) adp5061_get_max_voltage() argument
276 adp5061_set_max_voltage(struct adp5061_state *st, int val) adp5061_set_max_voltage() argument
297 adp5061_set_const_chg_vmax(struct adp5061_state *st, int val) adp5061_set_const_chg_vmax() argument
314 adp5061_set_const_chg_current(struct adp5061_state *st, int val) adp5061_set_const_chg_current() argument
335 adp5061_get_const_chg_current(struct adp5061_state *st, union power_supply_propval *val) adp5061_get_const_chg_current() argument
354 adp5061_get_prechg_current(struct adp5061_state *st, union power_supply_propval *val) adp5061_get_prechg_current() argument
370 adp5061_set_prechg_current(struct adp5061_state *st, int val) adp5061_set_prechg_current() argument
387 adp5061_get_vweak_th(struct adp5061_state *st, union power_supply_propval *val) adp5061_get_vweak_th() argument
403 adp5061_set_vweak_th(struct adp5061_state *st, int val) adp5061_set_vweak_th() argument
420 adp5061_get_chg_type(struct adp5061_state *st, union power_supply_propval *val) adp5061_get_chg_type() argument
439 adp5061_get_charger_status(struct adp5061_state *st, union power_supply_propval *val) adp5061_get_charger_status() argument
472 adp5061_get_battery_status(struct adp5061_state *st, union power_supply_propval *val) adp5061_get_battery_status() argument
501 adp5061_get_termination_current(struct adp5061_state *st, union power_supply_propval *val) adp5061_get_termination_current() argument
517 adp5061_set_termination_current(struct adp5061_state *st, int val) adp5061_set_termination_current() argument
532 adp5061_get_property(struct power_supply *psy, enum power_supply_property psp, union power_supply_propval *val) adp5061_get_property() argument
616 adp5061_set_property(struct power_supply *psy, enum power_supply_property psp, const union power_supply_propval *val) adp5061_set_property() argument
[all...] |
| /kernel/linux/linux-6.6/include/sound/ |
| H A D | emu8000_reg.h | 108 #define EMU8000_CPF_WRITE(emu, chan, val) \
109 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(0, (chan)), (val))
110 #define EMU8000_PTRX_WRITE(emu, chan, val) \
111 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(1, (chan)), (val))
112 #define EMU8000_CVCF_WRITE(emu, chan, val) \
113 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(2, (chan)), (val))
114 #define EMU8000_VTFT_WRITE(emu, chan, val) \
115 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(3, (chan)), (val))
116 #define EMU8000_PSST_WRITE(emu, chan, val) \
117 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(6, (chan)), (val))
[all...] |
| /kernel/linux/linux-5.10/sound/soc/ti/ |
| H A D | davinci-mcasp.h | 131 #define TXROT(val) (val)
133 #define TXSSZ(val) (val<<4)
134 #define TXPBIT(val) (val<<8)
135 #define TXPAD(val) (val<<13)
137 #define FSXDLY(val) (val<<1
[all...] |
| /kernel/linux/linux-6.6/sound/soc/ti/ |
| H A D | davinci-mcasp.h | 131 #define TXROT(val) (val)
133 #define TXSSZ(val) (val<<4)
134 #define TXPBIT(val) (val<<8)
135 #define TXPAD(val) (val<<13)
137 #define FSXDLY(val) (val<<1
[all...] |
| /kernel/linux/linux-5.10/drivers/hwtracing/coresight/ |
| H A D | coresight-etm3x-sysfs.c | 16 unsigned long val; in nr_addr_cmp_show() local
19 val = drvdata->nr_addr_cmp; in nr_addr_cmp_show()
20 return sprintf(buf, "%#lx\n", val); in nr_addr_cmp_show()
26 { unsigned long val; in nr_cntr_show() local
29 val = drvdata->nr_cntr; in nr_cntr_show()
30 return sprintf(buf, "%#lx\n", val); in nr_cntr_show()
37 unsigned long val; in nr_ctxid_cmp_show() local
40 val = drvdata->nr_ctxid_cmp; in nr_ctxid_cmp_show()
41 return sprintf(buf, "%#lx\n", val); in nr_ctxid_cmp_show()
48 unsigned long flags, val; in etmsr_show() local
70 unsigned long val; reset_store() local
98 unsigned long val; mode_show() local
111 unsigned long val; mode_store() local
183 unsigned long val; trigger_event_show() local
196 unsigned long val; trigger_event_store() local
213 unsigned long val; enable_event_show() local
226 unsigned long val; enable_event_store() local
243 unsigned long val; fifofull_level_show() local
256 unsigned long val; fifofull_level_store() local
273 unsigned long val; addr_idx_show() local
286 unsigned long val; addr_idx_store() local
313 unsigned long val; addr_single_show() local
337 unsigned long val; addr_single_store() local
434 unsigned long val; addr_start_show() local
458 unsigned long val; addr_start_store() local
488 unsigned long val; addr_stop_show() local
512 unsigned long val; addr_stop_store() local
541 unsigned long val; addr_acctype_show() local
557 unsigned long val; addr_acctype_store() local
576 unsigned long val; cntr_idx_show() local
589 unsigned long val; cntr_idx_store() local
614 unsigned long val; cntr_rld_val_show() local
630 unsigned long val; cntr_rld_val_store() local
649 unsigned long val; cntr_event_show() local
665 unsigned long val; cntr_event_store() local
684 unsigned long val; cntr_rld_event_show() local
700 unsigned long val; cntr_rld_event_store() local
720 u32 val; cntr_val_show() local
746 unsigned long val; cntr_val_store() local
765 unsigned long val; seq_12_event_show() local
778 unsigned long val; seq_12_event_store() local
794 unsigned long val; seq_21_event_show() local
807 unsigned long val; seq_21_event_store() local
823 unsigned long val; seq_23_event_show() local
836 unsigned long val; seq_23_event_store() local
852 unsigned long val; seq_31_event_show() local
865 unsigned long val; seq_31_event_store() local
881 unsigned long val; seq_32_event_show() local
894 unsigned long val; seq_32_event_store() local
910 unsigned long val; seq_13_event_show() local
923 unsigned long val; seq_13_event_store() local
939 unsigned long val, flags; seq_curr_state_show() local
966 unsigned long val; seq_curr_state_store() local
986 unsigned long val; ctxid_idx_show() local
999 unsigned long val; ctxid_idx_store() local
1025 unsigned long val; ctxid_pid_show() local
1079 unsigned long val; ctxid_mask_show() local
1099 unsigned long val; ctxid_mask_store() local
1122 unsigned long val; sync_freq_show() local
1135 unsigned long val; sync_freq_store() local
1151 unsigned long val; timestamp_event_show() local
1164 unsigned long val; timestamp_event_store() local
1180 int val; cpu_show() local
1192 unsigned long val; traceid_show() local
1205 unsigned long val; traceid_store() local
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/panel/ |
| H A D | panel-abt-y030xx067a.c | 23 #define REG00_VBRT_CTRL(val) (val)
25 #define REG01_COM_DC(val) (val)
27 #define REG02_DA_CONTRAST(val) (val)
28 #define REG02_VESA_SEL(val) ((val) << 5)
31 #define REG03_VPOSITION(val) (val)
[all...] |
| /kernel/linux/linux-5.10/drivers/remoteproc/ |
| H A D | qcom_q6v5_wcss.c | 103 u32 val; in q6v5_wcss_reset() local
107 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
108 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; in q6v5_wcss_reset()
109 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
112 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
113 val |= 0x1; in q6v5_wcss_reset()
114 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
118 val, !(val & BIT(31)), 1, in q6v5_wcss_reset()
126 val in q6v5_wcss_reset()
245 unsigned int val; q6v5_wcss_halt_axi_port() local
277 u32 val; q6v5_wcss_powerdown() local
323 u32 val; q6v5_q6_powerdown() local
[all...] |
| /kernel/linux/linux-5.10/drivers/pci/controller/dwc/ |
| H A D | pcie-tegra194.c | 341 u16 val; in apply_bad_link_workaround() local
348 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in apply_bad_link_workaround()
349 if (val & PCI_EXP_LNKSTA_LBMS) { in apply_bad_link_workaround()
350 current_link_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val); in apply_bad_link_workaround()
353 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
355 val &= ~PCI_EXP_LNKCTL2_TLS; in apply_bad_link_workaround()
356 val |= PCI_EXP_LNKCTL2_TLS_2_5GT; in apply_bad_link_workaround()
358 PCI_EXP_LNKCTL2, val); in apply_bad_link_workaround()
360 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
362 val | in apply_bad_link_workaround()
374 u32 val, status_l0, status_l1; tegra_pcie_rp_irq_handler() local
442 u32 val; pex_ep_event_hot_rst_done() local
470 u32 val, speed; tegra_pcie_ep_irq_thread() local
561 tegra_pcie_dw_rd_own_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) tegra_pcie_dw_rd_own_conf() argument
578 tegra_pcie_dw_wr_own_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) tegra_pcie_dw_wr_own_conf() argument
602 u32 val; disable_aspm_l11() local
611 u32 val; disable_aspm_l12() local
620 u32 val; event_counter_prog() local
637 u32 val; aspm_state_cnt() local
669 u32 val; init_host_aspm() local
710 u32 val; tegra_pcie_enable_system_interrupts() local
747 u32 val; tegra_pcie_enable_legacy_interrupts() local
768 u32 val; tegra_pcie_enable_msi_interrupts() local
810 u32 val, offset, i; config_gen3_gen4_eq_presets() local
864 u32 val; tegra_pcie_prepare_host() local
932 u32 val, tmp, offset, speed; tegra_pcie_dw_host_init() local
994 u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); tegra_pcie_dw_link_up() local
1322 u32 val; tegra_pcie_config_controller() local
1489 u32 val; tegra_pcie_try_link_l2() local
1621 u32 val; pex_ep_event_pex_rst_assert() local
1663 u32 val; pex_ep_event_pex_rst_deassert() local
2208 u32 val; tegra_pcie_dw_suspend_late() local
2270 u32 val; tegra_pcie_dw_resume_early() local
[all...] |
| /kernel/linux/linux-5.10/drivers/hwmon/ |
| H A D | hwmon-vid.c | 65 * val is the 4-bit or more VID code.
69 int vid_from_reg(int val, u8 vrm) in vid_from_reg() argument
77 val &= 0x3f; in vid_from_reg()
78 if ((val & 0x1f) == 0x1f) in vid_from_reg()
80 if ((val & 0x1f) <= 0x09 || val == 0x0a) in vid_from_reg()
81 vid = 1087500 - (val & 0x1f) * 25000; in vid_from_reg()
83 vid = 1862500 - (val & 0x1f) * 25000; in vid_from_reg()
84 if (val & 0x20) in vid_from_reg()
90 val in vid_from_reg()
[all...] |
| /kernel/linux/linux-6.6/drivers/hwmon/ |
| H A D | hwmon-vid.c | 65 * val is the 4-bit or more VID code.
69 int vid_from_reg(int val, u8 vrm) in vid_from_reg() argument
77 val &= 0x3f; in vid_from_reg()
78 if ((val & 0x1f) == 0x1f) in vid_from_reg()
80 if ((val & 0x1f) <= 0x09 || val == 0x0a) in vid_from_reg()
81 vid = 1087500 - (val & 0x1f) * 25000; in vid_from_reg()
83 vid = 1862500 - (val & 0x1f) * 25000; in vid_from_reg()
84 if (val & 0x20) in vid_from_reg()
90 val in vid_from_reg()
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
| H A D | intel_dpio_phy.c | 272 u32 val; in bxt_ddi_phy_set_signal_level() local
282 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch)); in bxt_ddi_phy_set_signal_level()
283 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); in bxt_ddi_phy_set_signal_level()
284 intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
286 val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
287 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); in bxt_ddi_phy_set_signal_level()
288 val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT; in bxt_ddi_phy_set_signal_level()
289 intel_de_write(dev_priv, BXT_PORT_TX_DW2_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
291 val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
292 val in bxt_ddi_phy_set_signal_level()
342 u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy)); bxt_get_grc() local
360 u32 val; _bxt_ddi_phy_init() local
456 u32 val; bxt_ddi_phy_uninit() local
502 u32 val; __phy_reg_verify_state() local
607 u32 val = intel_de_read(dev_priv, bxt_ddi_phy_set_lane_optim_mask() local
637 u32 val = intel_de_read(dev_priv, bxt_ddi_phy_get_lane_lat_optim_mask() local
657 u32 val; chv_set_phy_signal_level() local
752 u32 val; chv_data_lane_soft_reset() local
799 u32 val; chv_phy_pre_pll_enable() local
879 u32 val; chv_phy_pre_encoder_enable() local
965 u32 val; chv_phy_post_pll_disable() local
1060 u32 val; vlv_phy_pre_encoder_enable() local
[all...] |
| /kernel/linux/linux-6.6/drivers/accel/ivpu/ |
| H A D | ivpu_hw_40xx.c | 163 u32 val; in ivpu_pll_cmd_send() local
171 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0); in ivpu_pll_cmd_send()
172 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, MIN_RATIO, min_ratio, val); in ivpu_pll_cmd_send()
173 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, MAX_RATIO, max_ratio, val); in ivpu_pll_cmd_send()
174 REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, val); in ivpu_pll_cmd_send()
176 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1); in ivpu_pll_cmd_send()
177 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, TARGET_RATIO, target_ratio, val); in ivpu_pll_cmd_send()
270 u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_RST_EN); ivpu_boot_host_ss_rst_drive() local
287 u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_CLK_EN); ivpu_boot_host_ss_clk_drive() local
304 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN); ivpu_boot_noc_qreqn_check() local
314 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QACCEPTN); ivpu_boot_noc_qacceptn_check() local
324 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QDENY); ivpu_boot_noc_qdeny_check() local
334 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN); ivpu_boot_top_noc_qrenqn_check() local
345 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QACCEPTN); ivpu_boot_top_noc_qacceptn_check() local
356 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QDENY); ivpu_boot_top_noc_qdeny_check() local
367 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_IDLE_GEN); ivpu_boot_idle_gen_drive() local
403 u32 val; ivpu_boot_host_ss_axi_drive() local
440 u32 val; ivpu_boot_host_ss_top_noc_drive() local
472 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0); ivpu_boot_pwr_island_trickle_drive() local
487 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0); ivpu_boot_pwr_island_drive() local
511 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0); ivpu_boot_pwr_island_isolation_drive() local
523 u32 val = REGV_RD32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES); ivpu_boot_no_snoop_enable() local
534 u32 val = REGV_RD32(VPU_40XX_HOST_IF_TBU_MMUSSIDV); ivpu_boot_tbu_mmu_enable() local
548 u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN); ivpu_boot_cpu_noc_qacceptn_check() local
558 u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QDENY); ivpu_boot_cpu_noc_qdeny_check() local
601 u32 val; ivpu_boot_soc_cpu_drive() local
631 u32 val; ivpu_boot_soc_cpu_boot() local
657 u32 val; ivpu_boot_d0i3_drive() local
740 u32 val; ivpu_hw_40xx_reset() local
791 u32 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS); ivpu_hw_40xx_profiling_freq_reg_set() local
809 u32 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS); ivpu_hw_40xx_clock_relinquish_disable() local
883 u32 val; ivpu_hw_40xx_is_idle() local
915 u32 val; ivpu_hw_40xx_wdt_disable() local
957 u32 val = REG_FLD(VPU_40XX_CPU_SS_DOORBELL_0, SET); ivpu_hw_40xx_reg_db_set() local
[all...] |