Lines Matching refs:val
46 static int skl_get_dimm_size(u16 val)
48 return val & SKL_DRAM_SIZE_MASK;
51 static int skl_get_dimm_width(u16 val)
53 if (skl_get_dimm_size(val) == 0)
56 switch (val & SKL_DRAM_WIDTH_MASK) {
60 val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
61 return 8 << val;
63 MISSING_CASE(val);
68 static int skl_get_dimm_ranks(u16 val)
70 if (skl_get_dimm_size(val) == 0)
73 val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
75 return val + 1;
79 static int cnl_get_dimm_size(u16 val)
81 return (val & CNL_DRAM_SIZE_MASK) / 2;
84 static int cnl_get_dimm_width(u16 val)
86 if (cnl_get_dimm_size(val) == 0)
89 switch (val & CNL_DRAM_WIDTH_MASK) {
93 val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
94 return 8 << val;
96 MISSING_CASE(val);
101 static int cnl_get_dimm_ranks(u16 val)
103 if (cnl_get_dimm_size(val) == 0)
106 val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
108 return val + 1;
121 int channel, char dimm_name, u16 val)
124 dimm->size = cnl_get_dimm_size(val);
125 dimm->width = cnl_get_dimm_width(val);
126 dimm->ranks = cnl_get_dimm_ranks(val);
128 dimm->size = skl_get_dimm_size(val);
129 dimm->width = skl_get_dimm_width(val);
130 dimm->ranks = skl_get_dimm_ranks(val);
142 int channel, u32 val)
145 channel, 'L', val & 0xffff);
147 channel, 'S', val >> 16);
184 u32 val;
187 val = intel_uncore_read(&i915->uncore,
189 ret = skl_dram_get_channel_info(i915, &ch0, 0, val);
193 val = intel_uncore_read(&i915->uncore,
195 ret = skl_dram_get_channel_info(i915, &ch1, 1, val);
232 u32 val;
234 val = intel_uncore_read(&i915->uncore,
237 switch (val & SKL_DRAM_DDR_TYPE_MASK) {
247 MISSING_CASE(val);
256 u32 mem_freq_khz, val;
267 val = intel_uncore_read(&i915->uncore,
269 mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
286 static int bxt_get_dimm_size(u32 val)
288 switch (val & BXT_DRAM_SIZE_MASK) {
300 MISSING_CASE(val);
305 static int bxt_get_dimm_width(u32 val)
307 if (!bxt_get_dimm_size(val))
310 val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
312 return 8 << val;
315 static int bxt_get_dimm_ranks(u32 val)
317 if (!bxt_get_dimm_size(val))
320 switch (val & BXT_DRAM_RANK_MASK) {
326 MISSING_CASE(val);
331 static enum intel_dram_type bxt_get_dimm_type(u32 val)
333 if (!bxt_get_dimm_size(val))
336 switch (val & BXT_DRAM_TYPE_MASK) {
346 MISSING_CASE(val);
351 static void bxt_get_dimm_info(struct dram_dimm_info *dimm, u32 val)
353 dimm->width = bxt_get_dimm_width(val);
354 dimm->ranks = bxt_get_dimm_ranks(val);
360 dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm) / 8;
367 u32 mem_freq_khz, val;
371 val = intel_uncore_read(&i915->uncore, BXT_P_CR_MC_BIOS_REQ_0_0_0);
372 mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
375 dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
394 val = intel_uncore_read(&i915->uncore, BXT_D_CR_DRP0_DUNIT(i));
395 if (val == 0xFFFFFFFF)
400 bxt_get_dimm_info(&dimm, val);
401 type = bxt_get_dimm_type(val);
440 u32 val = 0;
446 &val, NULL);
451 switch (val & 0xf) {
465 MISSING_CASE(val & 0xf);
469 switch (val & 0xf) {
483 MISSING_CASE(val & 0xf);
488 dram_info->num_channels = (val & 0xf0) >> 4;
489 dram_info->num_qgv_points = (val & 0xf00) >> 8;