Lines Matching refs:val
206 u32 val;
209 val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);
210 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0);
211 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val);
212 writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
214 val = readl_relaxed(base + TEGRA_USB_PORTSC1);
215 val &= ~TEGRA_PORTSC1_RWC_BITS;
216 val &= ~TEGRA_USB_PORTSC1_PTS(~0);
217 val |= TEGRA_USB_PORTSC1_PTS(pts_val);
218 writel_relaxed(val, base + TEGRA_USB_PORTSC1);
225 u32 val;
228 val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);
230 val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD;
232 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD;
233 writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
235 val = readl_relaxed(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;
237 val |= TEGRA_USB_PORTSC1_PHCD;
239 val &= ~TEGRA_USB_PORTSC1_PHCD;
240 writel_relaxed(val, base + TEGRA_USB_PORTSC1);
312 u32 val;
322 val = readl_relaxed(base + UTMIP_BIAS_CFG0);
323 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
326 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) |
330 val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level);
331 val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level);
332 val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level);
334 writel_relaxed(val, base + UTMIP_BIAS_CFG0);
347 u32 val;
363 val = readl_relaxed(base + UTMIP_BIAS_CFG0);
364 val |= UTMIP_OTGPD | UTMIP_BIASPD;
365 writel_relaxed(val, base + UTMIP_BIAS_CFG0);
386 u32 val;
397 val = readl_relaxed(base + USB_SUSP_CTRL);
398 val |= USB_SUSP_SET;
399 writel_relaxed(val, base + USB_SUSP_CTRL);
403 val = readl_relaxed(base + USB_SUSP_CTRL);
404 val &= ~USB_SUSP_SET;
405 writel_relaxed(val, base + USB_SUSP_CTRL);
418 u32 val;
430 val = readl_relaxed(base + USB_SUSP_CTRL);
431 val |= USB_SUSP_CLR;
432 writel_relaxed(val, base + USB_SUSP_CTRL);
436 val = readl_relaxed(base + USB_SUSP_CTRL);
437 val &= ~USB_SUSP_CLR;
438 writel_relaxed(val, base + USB_SUSP_CTRL);
453 u32 val;
456 val = readl_relaxed(base + USB_SUSP_CTRL);
457 val |= UTMIP_RESET;
458 writel_relaxed(val, base + USB_SUSP_CTRL);
461 val = readl_relaxed(base + USB1_LEGACY_CTRL);
462 val |= USB1_NO_LEGACY_MODE;
463 writel_relaxed(val, base + USB1_LEGACY_CTRL);
466 val = readl_relaxed(base + UTMIP_TX_CFG0);
467 val |= UTMIP_FS_PREABMLE_J;
468 writel_relaxed(val, base + UTMIP_TX_CFG0);
470 val = readl_relaxed(base + UTMIP_HSRX_CFG0);
471 val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
472 val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
473 val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
474 writel_relaxed(val, base + UTMIP_HSRX_CFG0);
476 val = readl_relaxed(base + UTMIP_HSRX_CFG1);
477 val &= ~UTMIP_HS_SYNC_START_DLY(~0);
478 val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
479 writel_relaxed(val, base + UTMIP_HSRX_CFG1);
481 val = readl_relaxed(base + UTMIP_DEBOUNCE_CFG0);
482 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
483 val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
484 writel_relaxed(val, base + UTMIP_DEBOUNCE_CFG0);
486 val = readl_relaxed(base + UTMIP_MISC_CFG0);
487 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
488 writel_relaxed(val, base + UTMIP_MISC_CFG0);
491 val = readl_relaxed(base + UTMIP_MISC_CFG1);
492 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) |
494 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
496 writel_relaxed(val, base + UTMIP_MISC_CFG1);
498 val = readl_relaxed(base + UTMIP_PLL_CFG1);
499 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) |
501 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
503 writel_relaxed(val, base + UTMIP_PLL_CFG1);
507 val = readl_relaxed(base + USB_SUSP_CTRL);
508 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
509 writel_relaxed(val, base + USB_SUSP_CTRL);
511 val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
512 val &= ~UTMIP_PD_CHRG;
513 writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
515 val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
516 val |= UTMIP_PD_CHRG;
517 writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
524 val = readl_relaxed(base + UTMIP_XCVR_CFG0);
525 val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
531 val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
532 val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup);
534 val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
535 val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
538 val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
539 val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew);
540 val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew);
542 writel_relaxed(val, base + UTMIP_XCVR_CFG0);
544 val = readl_relaxed(base + UTMIP_XCVR_CFG1);
545 val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
547 val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
548 writel_relaxed(val, base + UTMIP_XCVR_CFG1);
550 val = readl_relaxed(base + UTMIP_BIAS_CFG1);
551 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
552 val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
553 writel_relaxed(val, base + UTMIP_BIAS_CFG1);
555 val = readl_relaxed(base + UTMIP_SPARE_CFG0);
557 val |= FUSE_SETUP_SEL;
559 val &= ~FUSE_SETUP_SEL;
560 writel_relaxed(val, base + UTMIP_SPARE_CFG0);
563 val = readl_relaxed(base + USB_SUSP_CTRL);
564 val |= UTMIP_PHY_ENABLE;
565 writel_relaxed(val, base + USB_SUSP_CTRL);
568 val = readl_relaxed(base + USB_SUSP_CTRL);
569 val &= ~UTMIP_RESET;
570 writel_relaxed(val, base + USB_SUSP_CTRL);
573 val = readl_relaxed(base + USB1_LEGACY_CTRL);
574 val &= ~USB1_VBUS_SENSE_CTL_MASK;
575 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
576 writel_relaxed(val, base + USB1_LEGACY_CTRL);
578 val = readl_relaxed(base + USB_SUSP_CTRL);
579 val &= ~USB_SUSP_SET;
580 writel_relaxed(val, base + USB_SUSP_CTRL);
586 val = readl_relaxed(base + USB_USBMODE);
587 val &= ~USB_USBMODE_MASK;
589 val |= USB_USBMODE_HOST;
591 val |= USB_USBMODE_DEVICE;
592 writel_relaxed(val, base + USB_USBMODE);
604 u32 val;
609 val = readl_relaxed(base + USB_SUSP_CTRL);
610 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
611 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
612 writel_relaxed(val, base + USB_SUSP_CTRL);
615 val = readl_relaxed(base + USB_SUSP_CTRL);
616 val |= UTMIP_RESET;
617 writel_relaxed(val, base + USB_SUSP_CTRL);
619 val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
620 val |= UTMIP_PD_CHRG;
621 writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
623 val = readl_relaxed(base + UTMIP_XCVR_CFG0);
624 val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
626 writel_relaxed(val, base + UTMIP_XCVR_CFG0);
628 val = readl_relaxed(base + UTMIP_XCVR_CFG1);
629 val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
631 writel_relaxed(val, base + UTMIP_XCVR_CFG1);
639 u32 val;
641 val = readl_relaxed(base + UTMIP_TX_CFG0);
642 val |= UTMIP_HS_DISCON_DISABLE;
643 writel_relaxed(val, base + UTMIP_TX_CFG0);
649 u32 val;
651 val = readl_relaxed(base + UTMIP_TX_CFG0);
652 val &= ~UTMIP_HS_DISCON_DISABLE;
653 writel_relaxed(val, base + UTMIP_TX_CFG0);
660 u32 val;
662 val = readl_relaxed(base + UTMIP_MISC_CFG0);
663 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
665 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
667 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
668 writel_relaxed(val, base + UTMIP_MISC_CFG0);
671 val = readl_relaxed(base + UTMIP_MISC_CFG0);
672 val |= UTMIP_DPDM_OBSERVE;
673 writel_relaxed(val, base + UTMIP_MISC_CFG0);
680 u32 val;
682 val = readl_relaxed(base + UTMIP_MISC_CFG0);
683 val &= ~UTMIP_DPDM_OBSERVE;
684 writel_relaxed(val, base + UTMIP_MISC_CFG0);
691 u32 val;
706 val = readl_relaxed(base + USB_SUSP_CTRL);
707 val |= UHSIC_RESET;
708 writel_relaxed(val, base + USB_SUSP_CTRL);
710 val = readl_relaxed(base + ULPI_TIMING_CTRL_0);
711 val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
712 writel_relaxed(val, base + ULPI_TIMING_CTRL_0);
714 val = readl_relaxed(base + USB_SUSP_CTRL);
715 val |= ULPI_PHY_ENABLE;
716 writel_relaxed(val, base + USB_SUSP_CTRL);
718 val = 0;
719 writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
721 val |= ULPI_DATA_TRIMMER_SEL(4);
722 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
723 val |= ULPI_DIR_TRIMMER_SEL(4);
724 writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
727 val |= ULPI_DATA_TRIMMER_LOAD;
728 val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
729 val |= ULPI_DIR_TRIMMER_LOAD;
730 writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
745 val = readl_relaxed(base + USB_SUSP_CTRL);
746 val |= USB_SUSP_CLR;
747 writel_relaxed(val, base + USB_SUSP_CTRL);
750 val = readl_relaxed(base + USB_SUSP_CTRL);
751 val &= ~USB_SUSP_CLR;
752 writel_relaxed(val, base + USB_SUSP_CTRL);