Lines Matching refs:val
103 u32 val;
107 val = readl(wcss->reg_base + Q6SS_RESET_REG);
108 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
109 writel(val, wcss->reg_base + Q6SS_RESET_REG);
112 val = readl(wcss->reg_base + Q6SS_XO_CBCR);
113 val |= 0x1;
114 writel(val, wcss->reg_base + Q6SS_XO_CBCR);
118 val, !(val & BIT(31)), 1,
126 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
127 val |= Q6SS_BHS_ON;
128 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
132 val |= Q6SS_LDO_BYP;
133 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
136 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
137 val &= ~Q6SS_CLAMP_QMC_MEM;
138 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
141 val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
142 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
145 val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
147 val |= BIT(i);
148 writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL);
154 val |= readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
158 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
159 val &= ~Q6SS_CLAMP_WL;
160 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
163 val &= ~Q6SS_CLAMP_IO;
164 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
167 val = readl(wcss->reg_base + Q6SS_RESET_REG);
168 val &= ~Q6SS_CORE_ARES;
169 writel(val, wcss->reg_base + Q6SS_RESET_REG);
172 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
173 val |= Q6SS_CLK_ENABLE;
174 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
177 val = readl(wcss->reg_base + Q6SS_RESET_REG);
178 val &= ~Q6SS_STOP_CORE;
179 writel(val, wcss->reg_base + Q6SS_RESET_REG);
245 unsigned int val;
249 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
250 if (!ret && val)
259 ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val);
260 if (ret || val || time_after(jiffies, timeout))
266 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
267 if (ret || !val)
277 u32 val;
283 val = readl(wcss->rmb_base + SSCAON_CONFIG);
284 val |= SSCAON_ENABLE;
285 writel(val, wcss->rmb_base + SSCAON_CONFIG);
288 val |= SSCAON_BUS_EN;
289 val &= ~SSCAON_BUS_MUX_MASK;
290 writel(val, wcss->rmb_base + SSCAON_CONFIG);
293 val |= BIT(1);
294 writel(val, wcss->rmb_base + SSCAON_CONFIG);
298 val, (val & 0xffff) == 0x400, 1000,
310 val = readl(wcss->rmb_base + SSCAON_CONFIG);
311 val &= ~SSCAON_ENABLE;
312 writel(val, wcss->rmb_base + SSCAON_CONFIG);
323 u32 val;
330 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
331 val &= ~Q6SS_CLK_ENABLE;
332 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
335 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
336 val |= Q6SS_CLAMP_IO;
337 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
340 val |= QDSS_BHS_ON;
341 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
344 val &= ~Q6SS_L2DATA_STBY_N;
345 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
348 val &= ~Q6SS_SLP_RET_N;
349 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
353 val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
354 val &= ~BIT(i);
355 writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL);
360 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
361 val |= Q6SS_CLAMP_QMC_MEM;
362 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
365 val &= ~Q6SS_BHS_ON;
366 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
371 val, !(val & BHS_EN_REST_ACK), 1000,