Lines Matching refs:val
341 u16 val;
348 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
349 if (val & PCI_EXP_LNKSTA_LBMS) {
350 current_link_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val);
353 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
355 val &= ~PCI_EXP_LNKCTL2_TLS;
356 val |= PCI_EXP_LNKCTL2_TLS_2_5GT;
358 PCI_EXP_LNKCTL2, val);
360 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
362 val |= PCI_EXP_LNKCTL_RL;
364 PCI_EXP_LNKCTL, val);
374 u32 val, status_l0, status_l1;
383 val = appl_readl(pcie, APPL_CAR_RESET_OVRD);
384 val &= ~APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N;
385 appl_writel(pcie, val, APPL_CAR_RESET_OVRD);
387 val = appl_readl(pcie, APPL_CAR_RESET_OVRD);
388 val |= APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N;
389 appl_writel(pcie, val, APPL_CAR_RESET_OVRD);
391 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
392 val |= PORT_LOGIC_SPEED_CHANGE;
393 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
419 val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
422 val |= PCIE_PL_CHK_REG_CHK_REG_COMPLETE;
426 val |= PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR;
430 val |= PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR;
432 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
433 val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_ERR_ADDR);
434 dev_err(pci->dev, "CDM Error Address Offset = 0x%08X\n", val);
442 u32 val;
461 val = appl_readl(pcie, APPL_CTRL);
462 val |= APPL_CTRL_LTSSM_EN;
463 appl_writel(pcie, val, APPL_CTRL);
470 u32 val, speed;
481 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub);
482 if (!(val & (PCI_L1SS_CAP_ASPM_L1_1 | PCI_L1SS_CAP_ASPM_L1_2)))
486 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
487 if (val & PCI_COMMAND_MASTER) {
491 val = 110 | (2 << PCI_LTR_SCALE_SHIFT) | LTR_MSG_REQ;
492 val |= (val << LTR_MST_NO_SNOOP_SHIFT);
493 appl_writel(pcie, val, APPL_LTR_MSG_1);
496 val = appl_readl(pcie, APPL_LTR_MSG_2);
497 val |= APPL_LTR_MSG_2_LTR_MSG_REQ_STATE;
498 appl_writel(pcie, val, APPL_LTR_MSG_2);
502 val = appl_readl(pcie, APPL_LTR_MSG_2);
503 if (!(val & APPL_LTR_MSG_2_LTR_MSG_REQ_STATE))
509 if (val & APPL_LTR_MSG_2_LTR_MSG_REQ_STATE)
562 int size, u32 *val)
571 *val = 0x00000000;
575 return pci_generic_config_read(bus, devfn, where, size, val);
579 int size, u32 val)
590 return pci_generic_config_write(bus, devfn, where, size, val);
602 u32 val;
604 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub);
605 val &= ~PCI_L1SS_CAP_ASPM_L1_1;
606 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);
611 u32 val;
613 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub);
614 val &= ~PCI_L1SS_CAP_ASPM_L1_2;
615 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);
620 u32 val;
622 val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid]);
623 val &= ~(EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT);
624 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
625 val |= event << EVENT_COUNTER_EVENT_SEL_SHIFT;
626 val |= EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
627 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val);
628 val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_data_offset[pcie->cid]);
630 return val;
637 u32 val;
659 val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
660 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
661 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val);
669 u32 val;
671 val = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS);
672 pcie->cfg_link_cap_l1sub = val + PCI_L1SS_CAP;
675 val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
676 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
677 dw_pcie_writel_dbi(pci, event_cntr_ctrl_offset[pcie->cid], val);
680 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub);
681 val &= ~(PCI_L1SS_CAP_CM_RESTORE_TIME | PCI_L1SS_CAP_P_PWR_ON_VALUE);
682 val |= (pcie->aspm_cmrt << 8);
683 val |= (pcie->aspm_pwr_on_t << 19);
684 dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val);
687 val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
688 val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;
689 val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT);
690 val |= PORT_AFR_ENTER_ASPM;
691 dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
710 u32 val;
713 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
714 val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN;
715 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
717 val = appl_readl(pcie, APPL_INTR_EN_L1_0_0);
718 val |= APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN;
719 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
722 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
723 val |= APPL_INTR_EN_L0_0_CDM_REG_CHK_INT_EN;
724 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
726 val = appl_readl(pcie, APPL_INTR_EN_L1_18);
727 val |= APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR;
728 val |= APPL_INTR_EN_L1_18_CDM_REG_CHK_LOGIC_ERR;
729 appl_writel(pcie, val, APPL_INTR_EN_L1_18);
747 u32 val;
750 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
751 val |= APPL_INTR_EN_L0_0_SYS_INTR_EN;
752 val |= APPL_INTR_EN_L0_0_INT_INT_EN;
753 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
755 val = appl_readl(pcie, APPL_INTR_EN_L1_8_0);
756 val |= APPL_INTR_EN_L1_8_INTX_EN;
757 val |= APPL_INTR_EN_L1_8_AUTO_BW_INT_EN;
758 val |= APPL_INTR_EN_L1_8_BW_MGT_INT_EN;
760 val |= APPL_INTR_EN_L1_8_AER_INT_EN;
761 appl_writel(pcie, val, APPL_INTR_EN_L1_8_0);
768 u32 val;
773 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
774 val |= APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN;
775 val |= APPL_INTR_EN_L0_0_MSI_RCV_INT_EN;
776 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
810 u32 val, offset, i;
814 val = dw_pcie_readw_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2));
815 val &= ~CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK;
816 val |= GEN3_GEN4_EQ_PRESET_INIT;
817 val &= ~CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK;
818 val |= (GEN3_GEN4_EQ_PRESET_INIT <<
820 dw_pcie_writew_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2), val);
825 val = dw_pcie_readb_dbi(pci, offset + i);
826 val &= ~PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK;
827 val |= GEN3_GEN4_EQ_PRESET_INIT;
828 val &= ~PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK;
829 val |= (GEN3_GEN4_EQ_PRESET_INIT <<
831 dw_pcie_writeb_dbi(pci, offset + i, val);
834 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
835 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
836 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
838 val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
839 val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK;
840 val |= (0x3ff << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT);
841 val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK;
842 dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val);
844 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
845 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
846 val |= (0x1 << GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT);
847 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
849 val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
850 val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK;
851 val |= (0x360 << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT);
852 val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK;
853 dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val);
855 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
856 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
857 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
864 u32 val;
866 val = dw_pcie_readl_dbi(pci, PCI_IO_BASE);
867 val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8);
868 dw_pcie_writel_dbi(pci, PCI_IO_BASE, val);
870 val = dw_pcie_readl_dbi(pci, PCI_PREF_MEMORY_BASE);
871 val |= CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE;
872 val |= CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE;
873 dw_pcie_writel_dbi(pci, PCI_PREF_MEMORY_BASE, val);
878 val = dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT);
879 val &= ~(AMBA_ERROR_RESPONSE_CRS_MASK << AMBA_ERROR_RESPONSE_CRS_SHIFT);
880 val |= (AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 <<
882 dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val);
885 val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP);
886 val &= ~PCI_EXP_LNKCAP_MLW;
887 val |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, pcie->num_lanes);
888 dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val);
894 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
895 val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
896 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
899 val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
900 val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;
901 dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val);
909 val = appl_readl(pcie, APPL_PINMUX);
910 val &= ~APPL_PINMUX_PEX_RST;
911 appl_writel(pcie, val, APPL_PINMUX);
916 val = appl_readl(pcie, APPL_CTRL);
917 val |= APPL_CTRL_LTSSM_EN;
918 appl_writel(pcie, val, APPL_CTRL);
921 val = appl_readl(pcie, APPL_PINMUX);
922 val |= APPL_PINMUX_PEX_RST;
923 appl_writel(pcie, val, APPL_PINMUX);
932 u32 val, tmp, offset, speed;
947 val = appl_readl(pcie, APPL_DEBUG);
948 val &= APPL_DEBUG_LTSSM_STATE_MASK;
949 val >>= APPL_DEBUG_LTSSM_STATE_SHIFT;
952 if (!(val == 0x11 && !tmp)) {
960 val = appl_readl(pcie, APPL_CTRL);
961 val &= ~APPL_CTRL_LTSSM_EN;
962 appl_writel(pcie, val, APPL_CTRL);
968 val = dw_pcie_readl_dbi(pci, offset + PCI_DLF_CAP);
969 val &= ~PCI_DLF_EXCHANGE_ENABLE;
970 dw_pcie_writel_dbi(pci, offset + PCI_DLF_CAP, val);
994 u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
996 return !!(val & PCI_EXP_LNKSTA_DLLLA);
1322 u32 val;
1356 val = appl_readl(pcie, APPL_CTRL);
1357 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
1359 val |= APPL_CTRL_HW_HOT_RST_EN;
1360 appl_writel(pcie, val, APPL_CTRL);
1378 val = appl_readl(pcie, APPL_CTRL);
1379 appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL);
1381 val = appl_readl(pcie, APPL_CFG_MISC);
1382 val |= (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT);
1383 appl_writel(pcie, val, APPL_CFG_MISC);
1386 val = appl_readl(pcie, APPL_PINMUX);
1387 val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN;
1388 val &= ~APPL_PINMUX_CLKREQ_OVERRIDE;
1389 appl_writel(pcie, val, APPL_PINMUX);
1489 u32 val;
1494 val = appl_readl(pcie, APPL_RADM_STATUS);
1495 val |= APPL_PM_XMT_TURNOFF_STATE;
1496 appl_writel(pcie, val, APPL_RADM_STATUS);
1498 return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val,
1499 val & APPL_DEBUG_PM_LINKST_IN_L2_LAT,
1621 u32 val;
1628 val = appl_readl(pcie, APPL_CTRL);
1629 val &= ~APPL_CTRL_LTSSM_EN;
1630 appl_writel(pcie, val, APPL_CTRL);
1632 ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,
1633 ((val & APPL_DEBUG_LTSSM_STATE_MASK) >>
1663 u32 val;
1718 val = appl_readl(pcie, APPL_DM_TYPE);
1719 val &= ~APPL_DM_TYPE_MASK;
1720 val |= APPL_DM_TYPE_EP;
1721 appl_writel(pcie, val, APPL_DM_TYPE);
1725 val = appl_readl(pcie, APPL_CTRL);
1726 val |= APPL_CTRL_SYS_PRE_DET_STATE;
1727 val |= APPL_CTRL_HW_HOT_RST_EN;
1728 appl_writel(pcie, val, APPL_CTRL);
1730 val = appl_readl(pcie, APPL_CFG_MISC);
1731 val |= APPL_CFG_MISC_SLV_EP_MODE;
1732 val |= (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT);
1733 appl_writel(pcie, val, APPL_CFG_MISC);
1735 val = appl_readl(pcie, APPL_PINMUX);
1736 val |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN;
1737 val |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE;
1738 appl_writel(pcie, val, APPL_PINMUX);
1747 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
1748 val |= APPL_INTR_EN_L0_0_SYS_INTR_EN;
1749 val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN;
1750 val |= APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN;
1751 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
1753 val = appl_readl(pcie, APPL_INTR_EN_L1_0_0);
1754 val |= APPL_INTR_EN_L1_0_0_HOT_RESET_DONE_INT_EN;
1755 val |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN;
1756 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
1761 val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
1762 val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;
1763 dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val);
1776 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
1777 val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
1778 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
1784 val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK);
1785 val |= MSIX_ADDR_MATCH_LOW_OFF_EN;
1786 dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_LOW_OFF, val);
1787 val = (upper_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK);
1788 dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_HIGH_OFF, val);
1799 val = appl_readl(pcie, APPL_CTRL);
1800 val |= APPL_CTRL_LTSSM_EN;
1801 appl_writel(pcie, val, APPL_CTRL);
2208 u32 val;
2214 val = appl_readl(pcie, APPL_CTRL);
2215 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
2217 val |= APPL_CTRL_HW_HOT_RST_EN;
2218 appl_writel(pcie, val, APPL_CTRL);
2270 u32 val;
2276 val = appl_readl(pcie, APPL_CTRL);
2277 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
2279 val |= APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST <<
2281 val &= ~APPL_CTRL_HW_HOT_RST_EN;
2282 appl_writel(pcie, val, APPL_CTRL);