Lines Matching refs:val
163 u32 val;
171 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0);
172 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, MIN_RATIO, min_ratio, val);
173 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, MAX_RATIO, max_ratio, val);
174 REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, val);
176 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1);
177 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, TARGET_RATIO, target_ratio, val);
178 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, EPP, epp, val);
179 REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, val);
181 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2);
182 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, CONFIG, config, val);
183 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, CDYN, cdyn, val);
184 REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, val);
186 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_CMD);
187 val = REG_SET_FLD(VPU_40XX_BUTTRESS_WP_REQ_CMD, SEND, val);
188 REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_CMD, val);
270 u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_RST_EN);
273 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val);
274 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val);
275 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val);
277 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val);
278 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val);
279 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val);
282 REGV_WR32(VPU_40XX_HOST_SS_CPR_RST_EN, val);
287 u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_CLK_EN);
290 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val);
291 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val);
292 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val);
294 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val);
295 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val);
296 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val);
299 REGV_WR32(VPU_40XX_HOST_SS_CPR_CLK_EN, val);
304 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN);
306 if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val))
314 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QACCEPTN);
316 if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QACCEPTN, TOP_SOCMMIO, exp_val, val))
324 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QDENY);
326 if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QDENY, TOP_SOCMMIO, exp_val, val))
334 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN);
336 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) ||
337 !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, exp_val, val))
345 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QACCEPTN);
347 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) ||
348 !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, HOSTIF_L2CACHE, exp_val, val))
356 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QDENY);
358 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) ||
359 !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, HOSTIF_L2CACHE, exp_val, val))
367 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_IDLE_GEN);
370 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val);
372 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val);
374 REGV_WR32(VPU_40XX_HOST_SS_AON_IDLE_GEN, val);
403 u32 val;
405 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN);
407 val = REG_SET_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);
409 val = REG_CLR_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);
410 REGV_WR32(VPU_40XX_HOST_SS_NOC_QREQN, val);
440 u32 val;
442 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN);
444 val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val);
445 val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
447 val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val);
448 val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
450 REGV_WR32(VPU_40XX_TOP_NOC_QREQN, val);
472 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0);
475 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val);
477 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val);
479 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val);
487 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0);
490 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val);
492 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val);
494 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, val);
511 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0);
514 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val);
516 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val);
518 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, val);
523 u32 val = REGV_RD32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES);
525 val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, SNOOP_OVERRIDE_EN, val);
526 val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AW_SNOOP_OVERRIDE, val);
527 val = REG_CLR_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AR_SNOOP_OVERRIDE, val);
529 REGV_WR32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, val);
534 u32 val = REGV_RD32(VPU_40XX_HOST_IF_TBU_MMUSSIDV);
536 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val);
537 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val);
538 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_AWMMUSSIDV, val);
539 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_ARMMUSSIDV, val);
540 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val);
541 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val);
543 REGV_WR32(VPU_40XX_HOST_IF_TBU_MMUSSIDV, val);
548 u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN);
550 if (!REG_TEST_FLD_NUM(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN, TOP_MMIO, exp_val, val))
558 u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QDENY);
560 if (!REG_TEST_FLD_NUM(VPU_40XX_CPU_SS_CPR_NOC_QDENY, TOP_MMIO, exp_val, val))
601 u32 val;
603 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QREQN);
605 val = REG_SET_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val);
607 val = REG_CLR_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val);
608 REGV_WR32(VPU_40XX_CPU_SS_CPR_NOC_QREQN, val);
631 u32 val;
644 val = REGV_RD32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO);
645 val = REG_SET_FLD(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, DONE, val);
646 REGV_WR32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val);
657 u32 val;
665 val = REGB_RD32(VPU_40XX_BUTTRESS_D0I3_CONTROL);
667 val = REG_SET_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, I3, val);
669 val = REG_CLR_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, I3, val);
670 REGB_WR32(VPU_40XX_BUTTRESS_D0I3_CONTROL, val);
740 u32 val;
748 val = REGB_RD32(VPU_40XX_BUTTRESS_IP_RESET);
749 val = REG_SET_FLD(VPU_40XX_BUTTRESS_IP_RESET, TRIGGER, val);
750 REGB_WR32(VPU_40XX_BUTTRESS_IP_RESET, val);
791 u32 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS);
794 val = REG_CLR_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, PERF_CLK, val);
796 val = REG_SET_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, PERF_CLK, val);
798 REGB_WR32(VPU_40XX_BUTTRESS_VPU_STATUS, val);
809 u32 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS);
811 val = REG_SET_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, DISABLE_CLK_RELINQUISH, val);
812 REGB_WR32(VPU_40XX_BUTTRESS_VPU_STATUS, val);
883 u32 val;
888 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS);
889 return REG_TEST_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, READY, val) &&
890 REG_TEST_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, IDLE, val);
915 u32 val;
923 val = REGV_RD32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG);
924 val = REG_CLR_FLD(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val);
925 REGV_WR32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, val);
957 u32 val = REG_FLD(VPU_40XX_CPU_SS_DOORBELL_0, SET);
959 REGV_WR32I(VPU_40XX_CPU_SS_DOORBELL_0, reg_stride, db_id, val);