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/kernel/linux/linux-5.10/drivers/regulator/
H A Dpfuze100-regulator.c228 #define PFUZE100_FIXED_REG(_chip, _name, base, voltage) \
238 .enable_reg = (base), \
243 #define PFUZE100_SW_REG(_chip, _name, base, min, max, step) \
254 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
256 .enable_reg = (base) + PFUZE100_MODE_OFFSET, \
259 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
264 #define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages) \
274 .vsel_reg = (base), \
276 .enable_reg = (base), \
281 #define PFUZE100_VGEN_REG(_chip, _name, base, mi
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/kernel/linux/linux-6.6/drivers/regulator/
H A Dpfuze100-regulator.c220 #define PFUZE100_FIXED_REG(_chip, _name, base, voltage) \
230 .enable_reg = (base), \
235 #define PFUZE100_SW_REG(_chip, _name, base, min, max, step) \
246 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
248 .enable_reg = (base) + PFUZE100_MODE_OFFSET, \
251 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
256 #define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages) \
266 .vsel_reg = (base), \
268 .enable_reg = (base), \
273 #define PFUZE100_VGEN_REG(_chip, _name, base, mi
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/third_party/libinput/test/
H A Dtest-misc.c123 struct libinput_event *base; in START_TEST() local
125 base = libinput_event_device_notify_get_base_event(dn); in START_TEST()
126 ck_assert(event == base); in START_TEST()
181 struct libinput_event *base; in START_TEST() local
183 base = libinput_event_pointer_get_base_event(p); in START_TEST()
184 ck_assert(event == base); in START_TEST()
233 struct libinput_event *base; in START_TEST() local
235 base = libinput_event_pointer_get_base_event(p); in START_TEST()
236 ck_assert(event == base); in START_TEST()
281 struct libinput_event *base; in START_TEST() local
333 struct libinput_event *base; START_TEST() local
387 struct libinput_event *base; START_TEST() local
435 struct libinput_event *base; START_TEST() local
478 struct libinput_event *base; START_TEST() local
523 struct libinput_event *base; START_TEST() local
[all...]
/third_party/node/deps/v8/src/objects/
H A Dstring.h10 #include "src/base/bits.h"
11 #include "src/base/export-template.h"
12 #include "src/base/strings.h"
130 base::Vector<const uint8_t> ToOneByteVector() const { in ToOneByteVector()
132 return base::Vector<const uint8_t>(onebyte_start, length_); in ToOneByteVector()
136 base::Vector<const base::uc16> ToUC16Vector() const { in ToUC16Vector()
138 return base::Vector<const base::uc16>(twobyte_start, length_); in ToUC16Vector()
141 base
[all...]
/third_party/skia/third_party/externals/harfbuzz/src/
H A Dhb-ot-color-cbdt-table.hh363 bool sanitize (hb_sanitize_context_t *c, const void *base) const in sanitize()
368 offsetToSubtable.sanitize (c, base, lastGlyphIndex - firstGlyphIndex + 1)); in sanitize()
371 const IndexSubtable* get_subtable (const void *base) const in get_subtable()
373 return &(base+offsetToSubtable); in get_subtable()
380 const void *base, in add_new_subtable()
389 auto *old_subtable = get_subtable (base); in add_new_subtable()
403 const IndexSubtable *next_subtable = next_record->get_subtable (base); in add_new_subtable()
448 const void *base, in add_new_record()
467 if (unlikely (!add_new_subtable (c, bitmap_size_context, &((*records)[records->length - 1]), lookup, base, start))) in add_new_record()
497 bool get_extents (hb_glyph_extents_t *extents, const void *base) cons
829 const void *base; get_extents() local
879 const void *base; reference_png() local
[all...]
/kernel/linux/linux-5.10/drivers/crypto/ux500/hash/
H A Dhash_core.c432 HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK); in hash_hw_write_key()
453 while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) in hash_hw_write_key()
458 while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) in hash_hw_write_key()
596 HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK); in hash_processblock()
623 HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK); in hash_messagepad()
635 while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) in hash_messagepad()
641 __func__, readl_relaxed(&device_data->base->din), in hash_messagepad()
642 readl_relaxed(&device_data->base->str) & HASH_STR_NBLW_MASK); in hash_messagepad()
645 __func__, readl_relaxed(&device_data->base->din), in hash_messagepad()
646 readl_relaxed(&device_data->base in hash_messagepad()
[all...]
/kernel/linux/linux-5.10/drivers/net/ethernet/qualcomm/emac/
H A Demac-mac.c263 mta = readl(adpt->base + EMAC_HASH_TAB_REG0 + (reg << 2)); in emac_mac_multicast_addr_set()
265 writel(mta, adpt->base + EMAC_HASH_TAB_REG0 + (reg << 2)); in emac_mac_multicast_addr_set()
270 writel(0, adpt->base + EMAC_HASH_TAB_REG0); in emac_mac_multicast_addr_clear()
271 writel(0, adpt->base + EMAC_HASH_TAB_REG1); in emac_mac_multicast_addr_clear()
286 mac = readl(adpt->base + EMAC_MAC_CTRL); in emac_mac_mode_config()
298 writel(mac, adpt->base + EMAC_MAC_CTRL); in emac_mac_mode_config()
306 adpt->base + EMAC_DESC_CTRL_1); in emac_mac_dma_rings_config()
309 adpt->base + EMAC_DESC_CTRL_8); in emac_mac_dma_rings_config()
312 adpt->base + EMAC_DESC_CTRL_9); in emac_mac_dma_rings_config()
316 adpt->base in emac_mac_dma_rings_config()
[all...]
/kernel/linux/linux-5.10/drivers/spi/
H A Dspi-stm32.c268 * @base: virtual memory area
288 * @phys_addr: SPI registers physical base address
294 void __iomem *base; member
356 writel_relaxed(readl_relaxed(spi->base + offset) | bits, in stm32_spi_set_bits()
357 spi->base + offset); in stm32_spi_set_bits()
363 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits, in stm32_spi_clr_bits()
364 spi->base + offset); in stm32_spi_clr_bits()
380 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP) in stm32h7_spi_get_fifo_size()
381 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_get_fifo_size()
419 cfg1 = readl_relaxed(spi->base in stm32h7_spi_get_bpw_mask()
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/kernel/linux/linux-6.6/drivers/net/ethernet/qualcomm/emac/
H A Demac-mac.c263 mta = readl(adpt->base + EMAC_HASH_TAB_REG0 + (reg << 2)); in emac_mac_multicast_addr_set()
265 writel(mta, adpt->base + EMAC_HASH_TAB_REG0 + (reg << 2)); in emac_mac_multicast_addr_set()
270 writel(0, adpt->base + EMAC_HASH_TAB_REG0); in emac_mac_multicast_addr_clear()
271 writel(0, adpt->base + EMAC_HASH_TAB_REG1); in emac_mac_multicast_addr_clear()
286 mac = readl(adpt->base + EMAC_MAC_CTRL); in emac_mac_mode_config()
298 writel(mac, adpt->base + EMAC_MAC_CTRL); in emac_mac_mode_config()
306 adpt->base + EMAC_DESC_CTRL_1); in emac_mac_dma_rings_config()
309 adpt->base + EMAC_DESC_CTRL_8); in emac_mac_dma_rings_config()
312 adpt->base + EMAC_DESC_CTRL_9); in emac_mac_dma_rings_config()
316 adpt->base in emac_mac_dma_rings_config()
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/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_display_debugfs.c116 fbdev_fb->base.width, in i915_gem_framebuffer_info()
117 fbdev_fb->base.height, in i915_gem_framebuffer_info()
118 fbdev_fb->base.format->depth, in i915_gem_framebuffer_info()
119 fbdev_fb->base.format->cpp[0] * 8, in i915_gem_framebuffer_info()
120 fbdev_fb->base.modifier, in i915_gem_framebuffer_info()
121 drm_framebuffer_read_refcount(&fbdev_fb->base)); in i915_gem_framebuffer_info()
122 i915_debugfs_describe_obj(m, intel_fb_obj(&fbdev_fb->base)); in i915_gem_framebuffer_info()
134 fb->base.width, in i915_gem_framebuffer_info()
135 fb->base.height, in i915_gem_framebuffer_info()
136 fb->base in i915_gem_framebuffer_info()
[all...]
H A Dskl_watermark.c210 struct drm_i915_private *i915 = to_i915(state->base.dev); in skl_sagv_pre_plane_update()
223 struct drm_i915_private *i915 = to_i915(state->base.dev); in skl_sagv_post_plane_update()
236 struct drm_i915_private *i915 = to_i915(state->base.dev); in icl_sagv_pre_plane_update()
252 WARN_ON(!new_bw_state->base.changed); in icl_sagv_pre_plane_update()
268 struct drm_i915_private *i915 = to_i915(state->base.dev); in icl_sagv_post_plane_update()
284 WARN_ON(!new_bw_state->base.changed); in icl_sagv_post_plane_update()
300 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_sagv_pre_plane_update()
320 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_sagv_post_plane_update()
341 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in skl_crtc_can_enable_sagv()
413 struct drm_i915_private *i915 = to_i915(crtc->base in intel_crtc_can_enable_sagv()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gem/
H A Di915_gem_ttm.c37 * @ttm: The base TTM page vector.
171 obj->base.size, flags); in i915_ttm_placement_from_obj()
177 obj->bo_offset, obj->base.size, flags); in i915_ttm_placement_from_obj()
302 ccs_pages = DIV_ROUND_UP(DIV_ROUND_UP(bo->base.size, in i915_ttm_tt_create()
310 __i915_refct_sgt_init(&i915_tt->cached_rsgt, bo->base.size, in i915_ttm_tt_create()
313 i915_tt->dev = obj->base.dev->dev; in i915_ttm_tt_create()
505 __shmem_writeback(obj->base.size, i915_tt->filp->f_mapping); in i915_ttm_shrink()
613 err = dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP, in i915_ttm_truncate()
657 return bman_res->used_visible_size == PFN_UP(bman_res->base.size); in i915_ttm_resource_mappable()
668 if (!kref_get_unless_zero(&obj->base in i915_ttm_io_mem_reserve()
695 unsigned long base; i915_ttm_io_mem_pfn() local
[all...]
/kernel/linux/linux-6.6/drivers/i2c/busses/
H A Di2c-qcom-geni.c174 writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL); in qcom_geni_i2c_conf()
177 writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG); in qcom_geni_i2c_conf()
182 writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS); in qcom_geni_i2c_conf()
187 u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0); in geni_i2c_err_misc()
188 u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS); in geni_i2c_err_misc()
189 u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS); in geni_i2c_err_misc()
190 u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS); in geni_i2c_err_misc()
191 u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN); in geni_i2c_err_misc()
195 rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT); in geni_i2c_err_misc()
196 tx_st = readl_relaxed(gi2c->se.base in geni_i2c_err_misc()
233 void __iomem *base = gi2c->se.base; geni_i2c_irq() local
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/third_party/node/deps/v8/src/diagnostics/mips/
H A Ddisasm-mips.cc14 // v8::base::EmbeddedVector<char, 256> buffer;
32 #include "src/base/platform/platform.h"
33 #include "src/base/strings.h"
34 #include "src/base/vector.h"
50 v8::base::Vector<char> out_buffer) in Decoder()
156 v8::base::Vector<char> out_buffer_;
245 out_buffer_pos_ += base::SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sa); in PrintSa()
251 out_buffer_pos_ += base::SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sa); in PrintLsaSa()
257 out_buffer_pos_ += base::SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sd); in PrintSd()
264 base in PrintSs1()
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/kernel/linux/linux-5.10/drivers/net/ethernet/cortina/
H A Dgemini.c152 void __iomem *base; member
575 dev_warn(geth->dev, "TX queue base is not aligned\n"); in gmac_setup_txqs()
708 qhdr = geth->base + TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id); in gmac_setup_rxq()
718 dev_warn(geth->dev, "RX queue base is not aligned\n"); in gmac_setup_rxq()
767 qhdr = geth->base + in gmac_cleanup_rxq()
885 rw.bits32 = readl(geth->base + GLOBAL_SWFQ_RWPTR_REG); in geth_fill_freeq()
919 writew(pn << fpp_order, geth->base + GLOBAL_SWFQ_RWPTR_REG + 2); in geth_fill_freeq()
943 dev_warn(geth->dev, "queue ring base is not aligned\n"); in geth_setup_freeq()
963 qt.bits32 = readl(geth->base + GLOBAL_QUEUE_THRESHOLD_REG); in geth_setup_freeq()
965 writel(qt.bits32, geth->base in geth_setup_freeq()
[all...]
/kernel/linux/linux-6.6/drivers/net/ethernet/cortina/
H A Dgemini.c151 void __iomem *base; member
574 dev_warn(geth->dev, "TX queue base is not aligned\n"); in gmac_setup_txqs()
707 qhdr = geth->base + TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id); in gmac_setup_rxq()
717 dev_warn(geth->dev, "RX queue base is not aligned\n"); in gmac_setup_rxq()
766 qhdr = geth->base + in gmac_cleanup_rxq()
884 rw.bits32 = readl(geth->base + GLOBAL_SWFQ_RWPTR_REG); in geth_fill_freeq()
918 writew(pn << fpp_order, geth->base + GLOBAL_SWFQ_RWPTR_REG + 2); in geth_fill_freeq()
942 dev_warn(geth->dev, "queue ring base is not aligned\n"); in geth_setup_freeq()
962 qt.bits32 = readl(geth->base + GLOBAL_QUEUE_THRESHOLD_REG); in geth_setup_freeq()
964 writel(qt.bits32, geth->base in geth_setup_freeq()
[all...]
/kernel/linux/linux-6.6/drivers/crypto/
H A Dsa2ul.c212 * @base: pointer to the base request
231 struct crypto_async_request *base; member
852 const char *name = crypto_tfm_alg_name(&tfm->base); in sa_cipher_cra_init()
906 crypto_skcipher_set_flags(child, tfm->base.crt_flags & in sa_cipher_setkey()
1049 req = container_of(rxd->req, struct skcipher_request, base); in sa_aes_dma_in_callback()
1099 gfp_flags = req->base->flags & CRYPTO_TFM_REQ_MAY_SLEEP ? in sa_run()
1253 rxd->req = (void *)req->base; in sa_run()
1301 struct crypto_alg *alg = req->base.tfm->__crt_alg; in sa_cipher_run()
1317 skcipher_request_set_callback(subreq, req->base in sa_cipher_run()
[all...]
/kernel/linux/linux-6.6/drivers/spi/
H A Dspi-imx.c97 void __iomem *base; member
154 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
176 writel(val, spi_imx->base + MXC_CSPITXDATA); \
309 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); in spi_imx_buf_rx_swap_u32()
345 val = readl(spi_imx->base + MXC_CSPIRXDATA); in spi_imx_buf_rx_swap()
377 writel(val, spi_imx->base + MXC_CSPITXDATA); in spi_imx_buf_tx_swap_u32()
405 writel(val, spi_imx->base + MXC_CSPITXDATA); in spi_imx_buf_tx_swap()
410 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA)); in mx53_ecspi_rx_target()
445 writel(val, spi_imx->base + MXC_CSPITXDATA); in mx53_ecspi_tx_target()
469 dev_err(spi_imx->dev, "cannot set clock freq: %u (base fre in mx51_ecspi_clkdiv()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Datom.c109 static uint32_t atom_iio_execute(struct atom_context *ctx, int base, in atom_iio_execute() argument
115 switch (CU8(base)) { in atom_iio_execute()
117 base++; in atom_iio_execute()
120 temp = ctx->card->reg_read(ctx->card, CU16(base + 1)); in atom_iio_execute()
121 base += 3; in atom_iio_execute()
124 ctx->card->reg_write(ctx->card, CU16(base + 1), temp); in atom_iio_execute()
125 base += 3; in atom_iio_execute()
129 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << in atom_iio_execute()
130 CU8(base + 2)); in atom_iio_execute()
131 base in atom_iio_execute()
1209 int base = CU16(ctx->cmd_table + 4 + 2 * index); amdgpu_atom_execute_table_locked() local
1291 atom_index_iio(struct atom_context *ctx, int base) atom_index_iio() argument
1462 int base; amdgpu_atom_parse() local
[all...]
/kernel/linux/linux-6.6/lib/
H A Diov_iter.c18 #define iterate_buf(i, n, base, len, off, __p, STEP) { \
21 base = __p + i->iov_offset; \
28 #define iterate_iovec(i, n, base, len, off, __p, STEP) { \
34 base = __p->iov_base + skip; \
49 #define iterate_bvec(i, n, base, len, off, p, STEP) { \
57 base = kaddr + offset % PAGE_SIZE; \
77 #define iterate_xarray(i, n, base, len, __off, STEP) { \
98 base = kmap_local_folio(folio, offset); \
101 kunmap_local(base); \
117 #define __iterate_and_advance(i, n, base, le
976 unsigned long base = (unsigned long)iov->iov_base; iov_iter_gap_alignment() local
[all...]
/third_party/node/deps/v8/src/compiler/
H A Dcode-assembler.cc9 #include "src/base/bits.h"
121 base::OS::DebugBreak();
245 base::EmbeddedVector<char, 1024> message; in GenerateCheckMaybeObjectIsObject()
303 factory()->InternalizeString(base::OneByteVector(str)); in StringConstant()
672 Node* CodeAssembler::Load(MachineType type, Node* base) { in Load() argument
673 return raw_assembler()->Load(type, base); in Load()
676 Node* CodeAssembler::Load(MachineType type, Node* base, Node* offset) { in Load() argument
677 return raw_assembler()->Load(type, base, offset); in Load()
680 TNode<Object> CodeAssembler::LoadFullTagged(Node* base) { in LoadFullTagged() argument
681 return BitcastWordToTagged(Load<RawPtrT>(base)); in LoadFullTagged()
684 LoadFullTagged(Node* base, TNode<IntPtrT> offset) LoadFullTagged() argument
691 AtomicLoad(MachineType type, AtomicMemoryOrder order, TNode<RawPtrT> base, TNode<WordT> offset) AtomicLoad() argument
699 AtomicLoad64(AtomicMemoryOrder order, TNode<RawPtrT> base, TNode<WordT> offset) AtomicLoad64() argument
757 UnalignedLoad(MachineType type, TNode<RawPtrT> base, TNode<WordT> offset) UnalignedLoad() argument
762 Store(Node* base, Node* value) Store() argument
817 Store(Node* base, Node* offset, Node* value) Store() argument
824 StoreEphemeronKey(Node* base, Node* offset, Node* value) StoreEphemeronKey() argument
830 StoreNoWriteBarrier(MachineRepresentation rep, Node* base, Node* value) StoreNoWriteBarrier() argument
837 StoreNoWriteBarrier(MachineRepresentation rep, Node* base, Node* offset, Node* value) StoreNoWriteBarrier() argument
846 UnsafeStoreNoWriteBarrier(MachineRepresentation rep, Node* base, Node* value) UnsafeStoreNoWriteBarrier() argument
851 UnsafeStoreNoWriteBarrier(MachineRepresentation rep, Node* base, Node* offset, Node* value) UnsafeStoreNoWriteBarrier() argument
859 StoreFullTaggedNoWriteBarrier(TNode<RawPtrT> base, TNode<Object> tagged_value) StoreFullTaggedNoWriteBarrier() argument
861 StoreNoWriteBarrier(MachineType::PointerRepresentation(), base, StoreFullTaggedNoWriteBarrier() local
865 StoreFullTaggedNoWriteBarrier(TNode<RawPtrT> base, TNode<IntPtrT> offset, TNode<Object> tagged_value) StoreFullTaggedNoWriteBarrier() argument
870 StoreNoWriteBarrier(MachineType::PointerRepresentation(), base, offset, StoreFullTaggedNoWriteBarrier() local
874 AtomicStore(MachineRepresentation rep, AtomicMemoryOrder order, TNode<RawPtrT> base, TNode<WordT> offset, TNode<Word32T> value) AtomicStore() argument
880 base, offset, value); AtomicStore() local
883 AtomicStore64(AtomicMemoryOrder order, TNode<RawPtrT> base, TNode<WordT> offset, TNode<UintPtrT> value, TNode<UintPtrT> value_high) AtomicStore64() argument
889 base, offset, value, value_high); AtomicStore64() local
920 AtomicCompareExchange(MachineType type, TNode<RawPtrT> base, TNode<WordT> offset, TNode<Word32T> old_value, TNode<Word32T> new_value) AtomicCompareExchange() argument
930 AtomicCompareExchange64( TNode<RawPtrT> base, TNode<WordT> offset, TNode<UintPtrT> old_value, TNode<UintPtrT> new_value, TNode<UintPtrT> old_value_high, TNode<UintPtrT> new_value_high) AtomicCompareExchange64() argument
[all...]
/kernel/linux/linux-5.10/drivers/bus/
H A Dtegra-gmi.c44 void __iomem *base; member
67 writel(gmi->snor_timing0, gmi->base + TEGRA_GMI_TIMING0); in tegra_gmi_enable()
68 writel(gmi->snor_timing1, gmi->base + TEGRA_GMI_TIMING1); in tegra_gmi_enable()
71 writel(gmi->snor_config, gmi->base + TEGRA_GMI_CONFIG); in tegra_gmi_enable()
81 config = readl(gmi->base + TEGRA_GMI_CONFIG); in tegra_gmi_disable()
83 writel(config, gmi->base + TEGRA_GMI_CONFIG); in tegra_gmi_disable()
219 gmi->base = devm_ioremap_resource(dev, res); in tegra_gmi_probe()
220 if (IS_ERR(gmi->base)) in tegra_gmi_probe()
221 return PTR_ERR(gmi->base); in tegra_gmi_probe()
/kernel/linux/linux-5.10/drivers/clk/mmp/
H A Dclk.h30 void __iomem *base; member
39 void __iomem *base, struct mmp_clk_factor_masks *masks,
130 const char *parent_name, void __iomem *base,
133 const char *parent_name, void __iomem *base, u32 enable_mask,
177 void __iomem *base, int size);
193 void __iomem *base, int size);
209 void __iomem *base, int size);
224 void __iomem *base, int size);
241 void __iomem *base, int size);
/kernel/linux/linux-5.10/arch/arm/mach-dove/
H A Dpcie.c28 void __iomem *base; member
52 orion_pcie_set_local_bus_nr(pp->base, sys->busnr); in dove_pcie_setup()
54 orion_pcie_setup(pp->base); in dove_pcie_setup()
109 ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val); in pcie_rd_conf()
127 ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val); in pcie_wr_conf()
189 static void __init add_pcie_port(int index, void __iomem *base) in add_pcie_port() argument
193 if (orion_pcie_link_up(base)) { in add_pcie_port()
204 pp->base = base; in add_pcie_port()
/kernel/linux/linux-5.10/drivers/ata/
H A Dpata_cs5530.c48 void __iomem *base = cs5530_port_base(ap); in cs5530_set_piomode() local
53 tuning = ioread32(base + 0x04); in cs5530_set_piomode()
58 base += 0x08; in cs5530_set_piomode()
60 iowrite32(cs5530_pio_timings[format][adev->pio_mode - XFER_PIO_0], base); in cs5530_set_piomode()
75 void __iomem *base = cs5530_port_base(ap); in cs5530_set_dmamode() local
80 tuning = ioread32(base + 0x04); in cs5530_set_dmamode()
101 iowrite32(timing, base + 0x04); in cs5530_set_dmamode()
107 iowrite32(tuning, base + 0x04); in cs5530_set_dmamode()
108 iowrite32(timing, base + 0x0C); in cs5530_set_dmamode()

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