Lines Matching refs:base
263 mta = readl(adpt->base + EMAC_HASH_TAB_REG0 + (reg << 2));
265 writel(mta, adpt->base + EMAC_HASH_TAB_REG0 + (reg << 2));
270 writel(0, adpt->base + EMAC_HASH_TAB_REG0);
271 writel(0, adpt->base + EMAC_HASH_TAB_REG1);
286 mac = readl(adpt->base + EMAC_MAC_CTRL);
298 writel(mac, adpt->base + EMAC_MAC_CTRL);
306 adpt->base + EMAC_DESC_CTRL_1);
309 adpt->base + EMAC_DESC_CTRL_8);
312 adpt->base + EMAC_DESC_CTRL_9);
316 adpt->base + EMAC_DESC_CTRL_0);
319 adpt->base + EMAC_DESC_CTRL_2);
321 adpt->base + EMAC_DESC_CTRL_5);
324 adpt->base + EMAC_DESC_CTRL_3);
326 adpt->base + EMAC_DESC_CTRL_6);
329 adpt->base + EMAC_DESC_CTRL_4);
331 writel(0, adpt->base + EMAC_DESC_CTRL_11);
333 /* Load all of the base addresses above and ensure that triggering HW to
336 writel(1, adpt->base + EMAC_INTER_SRAM_PART9);
345 JUMBO_TASK_OFFLOAD_THRESHOLD_BMSK, adpt->base + EMAC_TXQ_CTRL_1);
354 writel(val, adpt->base + EMAC_TXQ_CTRL_0);
355 emac_reg_update32(adpt->base + EMAC_TXQ_CTRL_2,
368 writel(val, adpt->base + EMAC_RXQ_CTRL_0);
370 val = readl(adpt->base + EMAC_RXQ_CTRL_1);
376 writel(val, adpt->base + EMAC_RXQ_CTRL_1);
378 val = readl(adpt->base + EMAC_RXQ_CTRL_2);
382 writel(val, adpt->base + EMAC_RXQ_CTRL_2);
384 val = readl(adpt->base + EMAC_RXQ_CTRL_3);
387 writel(val, adpt->base + EMAC_RXQ_CTRL_3);
419 writel(dma_ctrl, adpt->base + EMAC_DMA_CTRL);
434 writel(sta, adpt->base + EMAC_MAC_STA_ADDR0);
438 writel(sta, adpt->base + EMAC_MAC_STA_ADDR1);
456 adpt->base + EMAC_MAX_FRAM_LEN_CTRL);
462 val = readl(adpt->base + EMAC_AXI_MAST_CTRL);
465 writel(val, adpt->base + EMAC_AXI_MAST_CTRL);
466 writel(0, adpt->base + EMAC_CLK_GATE_CTRL);
467 writel(RX_UNCPL_INT_EN, adpt->base + EMAC_MISC_CTRL);
474 emac_reg_update32(adpt->base + EMAC_DMA_MAS_CTRL, 0, SOFT_RST);
478 emac_reg_update32(adpt->base + EMAC_DMA_MAS_CTRL, 0, INT_RD_CLR_EN);
487 emac_reg_update32(adpt->base + EMAC_TXQ_CTRL_0, 0, TXQ_EN);
490 emac_reg_update32(adpt->base + EMAC_RXQ_CTRL_0, 0, RXQ_EN);
493 mac = readl(adpt->base + EMAC_MAC_CTRL);
560 writel_relaxed(mac, adpt->base + EMAC_MAC_CTRL);
566 writel_relaxed(adpt->irq_mod, adpt->base + EMAC_IRQ_MOD_TIM_INIT);
568 IRQ_MODERATOR2_EN, adpt->base + EMAC_DMA_MAS_CTRL);
572 emac_reg_update32(adpt->base + EMAC_ATHR_HEADER_CTRL,
578 emac_reg_update32(adpt->base + EMAC_RXQ_CTRL_0, RXQ_EN, 0);
579 emac_reg_update32(adpt->base + EMAC_TXQ_CTRL_0, TXQ_EN, 0);
580 emac_reg_update32(adpt->base + EMAC_MAC_CTRL, TXEN | RXEN, 0);
909 emac_reg_update32(adpt->base + rx_q->produce_reg,
951 writel((u32)~DIS_INT, adpt->base + EMAC_INT_STATUS);
952 writel(adpt->irq.mask, adpt->base + EMAC_INT_MASK);
976 writel(DIS_INT, adpt->base + EMAC_INT_STATUS);
977 writel(0, adpt->base + EMAC_INT_MASK);
1098 reg = readl_relaxed(adpt->base + rx_q->consume_reg);
1161 emac_reg_update32(adpt->base + rx_q->process_reg,
1181 u32 reg = readl_relaxed(adpt->base + tx_q->consume_reg);
1476 emac_reg_update32(adpt->base + tx_q->produce_reg,