Lines Matching refs:base
97 void __iomem *base;
154 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
176 writel(val, spi_imx->base + MXC_CSPITXDATA); \
309 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
345 val = readl(spi_imx->base + MXC_CSPIRXDATA);
377 writel(val, spi_imx->base + MXC_CSPITXDATA);
405 writel(val, spi_imx->base + MXC_CSPITXDATA);
410 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA));
445 writel(val, spi_imx->base + MXC_CSPITXDATA);
469 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
499 writel(val, spi_imx->base + MX51_ECSPI_INT);
506 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
508 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
515 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
517 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
535 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
558 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
560 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
565 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG);
598 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
637 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
648 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
654 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
694 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
713 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
718 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
725 readl(spi_imx->base + MXC_CSPIRXDATA);
768 writel(val, spi_imx->base + MXC_CSPIINT);
775 reg = readl(spi_imx->base + MXC_CSPICTRL);
777 writel(reg, spi_imx->base + MXC_CSPICTRL);
817 writel(reg, spi_imx->base + MXC_CSPICTRL);
819 reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
824 writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
832 spi_imx->base + MX31_CSPI_DMAREG);
840 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
846 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
847 readl(spi_imx->base + MXC_CSPIRXDATA);
872 writel(val, spi_imx->base + MXC_CSPIINT);
879 reg = readl(spi_imx->base + MXC_CSPICTRL);
881 writel(reg, spi_imx->base + MXC_CSPICTRL);
912 writel(reg, spi_imx->base + MXC_CSPICTRL);
919 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
924 writel(1, spi_imx->base + MXC_RESET);
947 writel(val, spi_imx->base + MXC_CSPIINT);
954 reg = readl(spi_imx->base + MXC_CSPICTRL);
956 writel(reg, spi_imx->base + MXC_CSPICTRL);
982 writel(reg, spi_imx->base + MXC_CSPICTRL);
989 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
994 writel(1, spi_imx->base + MXC_RESET);
1133 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
1136 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
1635 readl(spi_imx->base + MXC_CSPIRXDATA);
1801 spi_imx->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1802 if (IS_ERR(spi_imx->base)) {
1803 ret = PTR_ERR(spi_imx->base);
1905 writel(0, spi_imx->base + MXC_CSPICTRL);